Hi EJ,

The fundamental limitation comes from the AD9371. Although the datasheet
specifies a wide reference clock input range, there are only certain
supported rates within the public side of their API (at least that I'm
aware of). These include the rates you mentioned from the KB.

Assuming the AD9371 allows it, adding a new MCR is not trivial and would
require a good deal of work across hardware, FPGA code, and MPM. The
fractional resampler sounds like a much better path forward, albeit
difficult right now.

Hopefully that explains some of the background on the chosen MCRs. Sorry it
wasn't exactly what you were hoping for!

-Daniel

On Wed, Oct 17, 2018 at 10:50 AM EJ Kreinar via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hi all,
>
> I'm working on an FPGA application on the n310/n300, and I'm bumping into
> a limitation of the master_clock_rate selection.... I'd like to be able to
> use sample rates in the FPGA of 2 MHz, 4 MHz, and 10 MHz, but none of these
> values are integer multiples of the supported rates (122.88e6, 125e6,
> 153.6e6 -- from here:
> https://kb.ettus.com/N300/N310_Getting_Started_Guides#Supported_Sample_Rates).
> This causes a problem in the FPGA since I would need a fractional
> resampler, which I dont currently have, unfortunately.
>
> What's the fundamental limitation of these master clock rates? I would
> have assumed that the AD9371-based architecture would have resulted in a
> wider variety of plausible clock rates, similar to the AD9361 on the E310.
> I havent found these limits yet in the software or FPGA, so any pointers
> where to look would be appreciated.
>
> As a follow up question, how feasible would it be to add a master clock
> rate of 120 MHz?? Any ideas where to make these changes? This would answer
> the mail for my sample rates of interest right now.
>
> Thanks!
> EJ
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>


-- 

Daniel Jepson

Digital Hardware Engineer

National Instruments



O: +1.512.683.6163

daniel.jep...@ni.com
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