Hi all, I'm working on an FPGA application on the n310/n300, and I'm bumping into a limitation of the master_clock_rate selection.... I'd like to be able to use sample rates in the FPGA of 2 MHz, 4 MHz, and 10 MHz, but none of these values are integer multiples of the supported rates (122.88e6, 125e6, 153.6e6 -- from here: https://kb.ettus.com/N300/N310_Getting_Started_Guides#Supported_Sample_Rates). This causes a problem in the FPGA since I would need a fractional resampler, which I dont currently have, unfortunately.
What's the fundamental limitation of these master clock rates? I would have assumed that the AD9371-based architecture would have resulted in a wider variety of plausible clock rates, similar to the AD9361 on the E310. I havent found these limits yet in the software or FPGA, so any pointers where to look would be appreciated. As a follow up question, how feasible would it be to add a master clock rate of 120 MHz?? Any ideas where to make these changes? This would answer the mail for my sample rates of interest right now. Thanks! EJ
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