Hi Ian,
> Ironically, the thing you described that I think is most likely to break the
> system is exporting those signal to the Mictor to look at them!
Hehe, well, there isn't much test points for me to probe them directly :)
But as you said :
- It wasn't working before
- I also built an image without my logic, but with those debug
signals routed and that works fine.
> I really can’t see how your new logic in radio could cause this (Unless it
> silently broke synthesis…did timing close ok?).
Yes me either, I'm really at a loss here :(
And I'm not even sure what would break in synthesis that would make me
observe the right SPI commands being sent and the catalina not
responding.
The synthesis & implementation worked fine and it reports all
constraints were met.
One additional result I just tried : My block uses both radio_clk and
bus_clk. Basically captures some samples to a BRAM then another part
will process them at a much higher clock rate.
I just tried feeding radio_clk to both side of the process and this
resulted in a working init. Although I'm not sure how that helps me.
I've followed all the rules for clock-domain crossing (and there is
very few signals crossing anyway) and even if I had screwed up
something, I can see how my logic would be misbehaving but not how
that would have any influence on the AD9361 init.
> Have you reordered any operations in the UHD driver etc doing your user_reg
> hack?
No. Also, using the exact same UHD but just a image I built but with
my logic disabled, the init works just fine.
Cheers,
Sylvain
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