Hi,
I'm working on a custom fpga image for the B210 running UHD 3.9.5 (and
associated fpga code).
I'm now faced with a problem that I cannot explain :
-- Initialize CODEC control...
terminate called after throwing an instance of 'uhd::runtime_error'
what(): RuntimeError: [ad9361_device_t] BBPLL not locked
When digging a bit further, it seems the AD9361 isn't responding to
SPI. I tried adding a read of the ID register 0x037 first thing in the
init, and it works fine in a vanilla build and doesn't work when my
logic is present.
But I also exported the catalina SPI signals and reset to the mictor
connector and plugged that to a logic analyzer and the signals sent
_to_ the catalina look identical, the only difference is that the miso
line stays at 0 with my custom image, and I don't see what I could
possibly have done that causes that ...
A few things I tried :
- Power with external power in case the added logic was causing USB
power to be insufficient
- Remove the logic for Radio 1 to save some logic and possibly power
- Slow the catalina SPI down
My custom logic doesn't modify anything in the control of the fpga, it
just "taps off" the sample_rx bus in radio_b200.v and process the
samples. The output of the block isn't even going anywhere yet, just
to a chipscope probe.
Anyone see how some seemingly unrelated logic could prevent the
catalina from talking to the fpga ?!?
Cheers,
Sylvain
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