Koen, 
Don’t feel bad….I designed the X310 Crossbar, and I had never heard the term 
RTR used until I read your email!

So to summarize the RFNoC concept, (since I’m no longer involved with the 
current implementation):

The “RTR” encompasses all the functionality that transports data between RFNoC 
compliant IP blocks, which include pre-designed DUC/DDC DSP “radio” blocks, and 
UDP/IP en/ decapsulation blocks that allow CHDR protocol packets to tunnel IP 
networks. You can also optionally add your own RFNoC blocks (which is kind of 
the point). 

From the prospective of the RFNoC user, the RTR should be largely transparent, 
data flows between blocks in the GRC flow graph and UHD driver functionality 
deals with encapsulating that in UDP/IP/CHDR when it transits a graph arc that 
bridges RFNoC and GNURadio. Like wise when data transits a graph arc between 
RFNoC blocks UHD behind the scenes has configured all the available RFNoC 
blocks with unique addresses (in the scope of CHDR) and the structure of the 
current graph (extracted from GRC). 

The actual RFNoC block is typically wrapped in a piece of boiler-plate Verilog 
called the NoC Shell that implements the CHDR transport protocol in H/W, and 
that, together with the configuration programmed by UHD routes the data between 
the various RFNoC blocks, without you (in theory) having to do any new FPGA 
work related to transport or connectivity.

The crossbar switch is simply the current H/W implementation for routing the 
addressed CHDR packets between blocks.

OK, so to the meat of your question…..

The above is the extent of the fully supported design flow in terms of Customer 
Support, beyond the scope of this you have to be more self reliant. FPGA savy 
designers have reworked the internals of X310 and other USRP’s extensively when 
they have needed to but it requires getting underneath the public UHD API at 
which point the “Source code becomes the documentation”. You can easily leave 
GNU Radio behind, the C++ and Python examples supplied with UHD demonstrate 
that, but pretty much nobody can do without UHD, as the low level driver 
functionality is pretty much a prerequisite to configure and operate the FPGA 
H/W.

If you are looking for suggestions beyond here you will probably have to share 
some details of how your own source code operates and what interfaces it has.

-Ian




> On May 23, 2018, at 1:55 AM, TIMMEN Koen via USRP-users 
> <usrp-users@lists.ettus.com> wrote:
> 
> Hello everyone,
>  
> Since a couple of months now, I’ve begun to work with FPGA development and 
> have been using RFNoC and the USRP X310 specifically. In other words, I’m 
> just starting to figure out this technology and still struggling with some of 
> the concepts used by the new USRP architecture and even more so the practical 
> implementation of it. I hope I’ll be able to get some clarification on these 
> subjects here.
>  
> As I understand, the aim of the USRP Architecture and RFNoC is to let 
> developers focus on creating their own IP (or CE), which can then be added as 
> a RFNoC block to an FPGA image. This image already contains by default the 
> structure revolving around a Radio Transport Router (RTR) that is described 
> in various resources, it supposedly uses the CHDR transport protocol to route 
> data between blocks.
>  
> However, when I look at the available source code, I am not able to recognize 
> this architecture anywhere. No RTR block and also, the RFNoC Getting Started 
> guide does not mention it. It does however mention the crossbar. Are these 
> two concepts one and the same?
>  
> Also, I was wondering how the connection between two blocks is created. As 
> far as I can see, this is handled on the background through the 
> gnuradio-companion interface. Is there a way for me to manage these 
> connections myself? Without the use of the gnuradio-companion?
>  
> Ultimately, I would like to use the X310 to generate some signals. For this I 
> already have source code in place. And I do not want to have to run gnuradio 
> every time. Is there a way to modify the standard FPGA image that is loaded 
> that allows me to achieve this? All source code should be available.. but I 
> have no idea how to get this in a Vivado project and get started doing this.
>  
> All online help I could find explains me how to create custom IP and use this 
> in combination with the target images provided, which then require me to use 
> gnuradio again. If someone could verify or correct my current understanding 
> of the project or perhaps point me to resources I overlooked, it would be 
> greatly appreciated. 
>  
> Kind regards,
>  
> Koen 
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