Were you able to make any further progress building the B210 FPGA code on
Windows with Cygwin?
While it should be possible to build the FPGA under Windows, you should
probably try it under Ubuntu 16.04, which should just work out-of-the-box.
--Neel Pandeya
On 8 April 2018 at 21:17, Yeo Jin Kuang Alvin (IA) via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Am I able to run make in Windows using Cygwin for ISE 14.7? I tried to run
> make PROJECT_ONLY=1 , and this is what I get.
>
>
>
> $ make PROJECT_ONLY=1
>
> /bin/sh: xtclsh: command not found
>
> ISE Version:
>
> make -f Makefile.b200.inc proj NAME=B200 DEVICE=XC6SLX75 EXTRA_DEFS=" "
>
> make[1]: Entering directory
> '/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff
>
>
> 6f1f9ae966edd531dc4b611d7/usrp3/top/b200'
>
> /bin/sh: xtclsh: command not found
>
> /bin/sh: xtclsh: command not found
>
> build-B200//b200.xise
>
> xtclsh
> /cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff6f1f9ae966edd531dc4b61
>
>
> 1d7/usrp3/top/tcl/ise_helper.tcl ""
>
> /bin/sh: xtclsh: command not found
>
> make[1]: *** [../Makefile.common:52: build-B200//b200.xise] Error 127
>
> make[1]: Leaving directory
> '/cygdrive/c/Users/WORK/Desktop/fpga-7c6bf35ce8f14ff6
>
>
> f1f9ae966edd531dc4b611d7/usrp3/top/b200'
>
> make: *** [Makefile:73: B200] Error 2
>
>
>
> ------------------------------------------------------------
> ------------------------------------------------------------
> ------------------------------------------------------
>
>
>
> I ran source C:/Xilinx/14.7/ISE_DS/settings64.bat and I got this
>
>
>
> $ source C:/Xilinx/14.7/ISE_DS/settings64.bat
>
> -bash: @echo: command not found
>
> -bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: syntax error near
> unexpected token `('
>
> -bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: `REM Copyright (c)
> 1995-201' Xilinx, Inc. All rights reserved.
>
>
>
>
>
> *From:* Robin Coxe [mailto:robin.c...@ettus.com]
> *Sent:* Monday, 9 April 2018 11:16 AM
> *To:* Yeo Jin Kuang Alvin (IA)
> *Cc:* usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] Ettus Code (FPGA) for USRP B210
>
>
>
> B200.v is the top level Verilog file. If you inspect this file, you will
> see that B200_core.v and B200_io.v are instantiated within it.
>
>
>
> All of our FPGA code is freely available-- please take some time to look
> through the files in the usrp3/lib directories here: https://github.com/
> EttusResearch/fpga/tree/maint/usrp3/lib
>
>
>
> -Robin
>
>
>
>
>
>
>
>
>
> On Mon, Apr 9, 2018 at 10:59 AM, Yeo Jin Kuang Alvin (IA) via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> Hi everyone,
>
>
>
> I want to use the ettus code for the USRP B210, however, may I know which
> is the Top file as I noticed there are 3 different ones. B200.v ,
> B200_core.v , B200_io.v. Tried to add the source file to Xilinx ISE 14.7
> but there are some files that I couldn’t find, eg. Gpif_sync, slave_fifo32,
> uart_timing_fifo etc.
>
>
>
> What are the essentials file and where do I find it?
>
>
>
> Thanks in advance!
>
>
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>
>
>
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