Hi,

Thanks for the reply!

If lets say I would like to bypass all these from the GPIF_D to the tx_codec_d 
and implement my own signal to the tx_codec_d straight, will I get the same 
output? Output going into DAC is the same as output transmitting out from DAC.

Second question is, must the clock rate of the DDS in the FPGA be the same as 
the master_clock_rate?

Thank you in advance!

From: Derek Kozel [mailto:derek.ko...@ettus.com]
Sent: Thursday, 26 April 2018 6:39 PM
To: Yeo Jin Kuang Alvin (IA)
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] B210 FPGA Code

Hello Yeo Jin Kuang Alvin,
I am not Ettus' expert in the B210 FPGA, but it would be highly unusual if 
there were arbitrary bit width changes. I believe that the GPIF bus is 16 bits 
of I and Q in parallel. The FX3 GPIF bus definition is included in the source 
and you can use Cypress's tools to look at the configuration of the bus in 
addition to the FPGA source code. There is considerable DSP implemented in the 
FPGA, including the decimation, interpolation, and frequency shifting 
operations. At minimum you would have to make changes to the UHD driver to 
remove support for those features if you bypass them.
My apologies if I've missed this in another email, but what is your goal with 
these changes?
Regards,
Derek

On Thu, Apr 26, 2018 at 10:18 AM, Yeo Jin Kuang Alvin (IA) via USRP-users 
<usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hi everyone!

For the FPGA source code written for b210, I noticed that the input to the 
GPIF_D that is 32 bits, and then in went through some FIFOs up converting to 64 
bits and then down to 12 bits output (tx_codec_d).

May I know what is the purpose of up converting and then down convert again?

Will it affect anything if I remove all these and just connect GPIF_D (32 bits) 
input and take 12 bits MSB (truncation) and connect directly to tx_codec_d (12 
bits) ?

Thanks in advance!

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