On 02/20/2018 10:08 AM, Francois Quitin via USRP-users wrote:
Dear Robin,
Thanks for the quick reply. Although the 180-degree ambiguity is
already good to know, what we are observing is really some rotation in
the IQ plane (not just an ambiguity).
Does the LO lock happens fast? Or should I wait for some time after
launching my GNURadio script for the PLL to lock?
Thanks,
François
It is unfortunately the case that the B2xx-mini series use a FPGA-based
DPLL to synchronize the internal clocks to an external clock reference.
This DPLL/FLL has some behavioral issues that mean that it cannot be
used for MIMO-type synchronization.
Now, in *your particular example*, you're hoping for perfect
synchronization in frequency and phase between a transmitter and receiver.
In the "real world", this never happens, which is why receiver logic
always includes modules for accounting for slight phase/frequency errors
between TX and RX, because it's nearly never the case that a TX and
an RX share a clock reference, so dealing with small phase/frequency
offsets is the job of the receiver DSP logic.
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