Hello Chris Yarp: Please do not remove any of the I/O for the PCIe interface (such as x300_pcie_int and LvFpga_Chinch_Interface) from the FPGA. Even if you're not using the PCIe interface, these modules are required. Please see the notice at the link below.
https://kb.ettus.com/X300/X310#FPGA_User_Modifications --​Neel Pandeya On 9 October 2017 at 10:31, Christopher Yarp via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello Everyone, > We are building a custom FPGA image using RFNoC targeting the x310 > platform. We are currently running out of FPGA resources and are looking > for ways to slim the base image down. We are not using the PCIe interface > and it looks like the PCIe IP (x300_pcie_int and LvFpga_Chinch_Interface) > use a non trivial amount of resources. I was looking into removing these > IP blocks but it appears that the schematics for the x310 ( > https://files.ettus.com/schematics/x300/x3xx.pdf) omits the pages > pertaining to the PCIe interface and the NI DAQ-STC3-BG chip. I would like > to avoid damaging any of the hardware and was wondering if anyone knows how > to properly terminate the lines that would normally be connected to the > PCIe IP? Does anyone know of any hazards removing this IP? Is the proper > initialization of the DAQ-STC3-BG required for the x310 to operate > correctly? > > Thanks, > Chris Yarp > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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