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1. DATE 2015 Students Competition 2. January TCAD Newsletter 3. DAC Designer Track 1 -------------------------------------------------------------------------------------------------------------------------------- DATE 2015 Students Competition Students Competition (March 9th, DATE 2015) Smart and Pervasive Tracking and Monitoring in the IoT Scenario Scenario ---------- Smartphones with Wi-Fi enabled periodically transmit Wi-Fi messages, even when not associated to a network. In this contest, we propose to develop a software system for passively tracking unmodified smartphones, based on such Wi-Fi detections. This system will rely only on common, off-the-shelf access point hardware to both collect and deliver detections. Setup and Evaluation -------------------------- Each registered team can have up to 3 members. The IoT contest organizers will provide in advance a map of the possibly assigned positions for the teams (with power plugs and WiFi internet access). Exact positions will be disclosed on the day of the contest (Monday, March 9th, at DATE week). Each team brings its own computer with the running tracking software and presents a poster with their solution (software engineering and algorithms). The teams are expected to use their own wireless interface to sniff the ‘hello packets’ of the smartphones. The evaluation of the proposed solutions will be performed with a set of controlled members (DATE Executive Committee members) who will transit across the area during the contest (MAC addresses to be known in advance). Specific tracking positions will be evaluated by the IoT coordinators. On site, the contest will take place on a 4 hours slot, which comprises 2 hours of installation – assignment of positions, final debug, … and 2 hours of real test. The evaluation will be done during these 2 hours. Each team will also have to come with a poster describing their technical solution. The DATE attendees are encouraged to come and discuss with the students during this time. The team with the highest score will win the competition. The price will be subsequently given on Wednesday, March 11th, lunch time, during the keynote talk. More information and Call for Participation can be found at: http://greendisc.dacya.ucm.es/ieee-ceda-1st-internet-of-things-iot/ Important Dates ------------------- Registration to the contest (send an email to the contest organizers with the personal data of the team components): January 15th, 2015 Description of the solution followed (4 pages report to be sent to conference organizers): 22nd February, 2015 Contest date (on DATE site): March 9th, 2015 Prizes ------- Winner: 1000 € prize + printed award 2nd team in classification: 500 € prize + printed award 3rd team in classification: printed award All participants will receive a Participation Diploma Organizers ------------- Jose L. Ayala – Complutense University of Madrid (Spain) jay...@ucm.es Pierre-Emmanuel Gaillardon, EPFL, Lausanne (Switzerland) pierre-emmanuel.gaillar...@epfl.ch With the sponsorship of IEEE CEDA (Council on Electronic Design Automation) CEDA Representative: David Atienza (VP of Conferences, EPFL) 2 -------------------------------------------------------------------------------------------------------------------------------- January TCAD Newsletter Placing you one click away from the best new CAD research! EDITORIAL http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6990721 REGULAR PAPERS EMBEDDED SECURITY Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures Kannan, S. ; Karimi, N. ; Sinanoglu, O. ; Karri, R. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6952995 Emerging nonvolatile memory devices such as phase change memories and memristors are replacing SRAM and DRAM. However, nonvolatile main memories (NVMM) are susceptible to probing attacks even when powered down. This way, they may compromise sensitive data such as passwords and keys that reside in the NVMM. To eliminate this vulnerability, we propose sneak-path encryption (SPE), a hardware intrinsic encryption technique for memristor-based NVMMs. SPE is instruction set architecture independent and has minimal impact on performance. SPE exploits the physical parameters, such as sneak-paths in crossbar memories, to encrypt the data stored in a memristor-based NVMM. SPE is resilient to a number of attacks that may be performed on NVMMs. We use a cycle accurate simulator to evaluate the performance impact of SPE-based NVMM and compare against other security techniques. SPE can secure an NVMM with a $sim 1.3$ % performance overhead. EMBEDDED SYSTEMS Garbage Collection for Low Performance Variation in NAND Flash Storage Systems Jung, S. ; Ho Song, Y. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6954423 In many NAND flash-memory storage systems, invalidated pages can occupy the storage space until being erased. In order to preserve sustained write performance and effective storage capacity, the flash translation layer (FTL) must recycle these pages through garbage collection (GC) operations. Many previous studies have investigated GC techniques, most of which have focused on the effective selection of victim blocks to reduce the operational overhead. However, methods to reduce the cost overhead of the victim selection process, as well as to improve the responsiveness of storage systems during GC, have not yet been explored. In this paper, therefore, we propose a novel GC mechanism, called link-based GC (LINK-GC), which provides fast victim selection and preemptive operation with small additional space overhead to existing page-mapped FTLs. In our experiments, when compared with a GC scheme based on an on-demand victim search, the proposed mechanism increases the average input–output operations per second (IOPS) by up to 15.8% and decreases the standard deviation of IOPS by up to 6.16 times. Additionally, the LINK-GC shows better performance than the existing preemptive GC techniques in terms of responsiveness to host requests. EMERGING TECHNOLOGIES Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction Luo, Y. ; Bhattacharya, B.B. ; Ho, T. ; Chakrabarty, K. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6923466 The amount of DNA strands available in a biological sample is a major limitation for many genomic bioanalyses. To amplify the traces of DNA strands, polymerase chain reaction (PCR) is widely used for conducting subsequent experiments. Compared to conventional instruments and analyzers, the execution of PCR on a digital microfluidic biochip (DMFB) can achieve short time-to-results, low reagent consumption, rapid heating/cooling rates, and high integration of multiple processing modules. However, the PCR biochip design methods in the literature are oblivious to the inherent randomness and complexity of bioanalyses, and they do not consider the interference among the neighboring devices and the cost of droplet transportation. We present an integrated design solution to optimize the complete PCR procedure, including: 1) DNA amplification and termination control; 2) resource placement that satisfies proximity constraints; and 3) droplet transportation. Based on the sensor feedback data, a statistical model is developed to optimize and control the DNA amplification sequence in real-time on a cyberphysical biochip. Next, we present a geometric algorithm for avoiding device interference and for reducing droplet routing cost. A novel optical sensing system is deployed based on the physical visibility of droplets. Simulation results for three laboratory protocols demonstrate that the proposed design method results in a compact layout and produces an execution sequence for efficient control of PCR operations on a cyberphysical DMFB. FPGAs AND RECONFIGURABLE COMPUTING Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing Broich, R. ; Grobler, H. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6928471 Current radar signal processors (RSPs) lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use an iterative design methodology to propose a novel soft-core streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional units each cycle. By explicitly specifying instruction-level parallelism and software pipelining, applications can fully exploit the available computational resources. The proposed architecture exceeds the clock cycle performance of a commercial high-end digital signal processor (DSP) processor by an average factor of 14 over a range of typical operating parameters in an RSP application. HIGH-LEVEL SYNTHESIS A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors Sierra, R. ; Carreras, C. ; Caffarena, G. ; Lopez Bario, C.A. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6936317 Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are commonplace in resource, latency, or power constrained designs. This paper describes and proves correct a formal method for accurate high-level casting of optimal adders and subtractors. The proposed approach allows for an early accurate estimation of resource usage which is then available for high-level decision-taking in the design flow. As a result, decoupling between high-level and low-level synthesis is achieved. Results concerning the impact of the approach on resource estimates and a discussion on the wide applicability of the method are presented. MODELING AND SIMULATION Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition Zhang, Z. ; Yang, X. ; Oseledets, I.V. ; Karniadakis, G.E. ; Daniel, L. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6954398 Hierarchical uncertainty quantification can reduce the computational cost of stochastic circuit simulation by employing spectral methods at different levels. This paper presents an efficient framework to simulate hierarchically some challenging stochastic circuits/systems that include high-dimensional subsystems. Due to the high parameter dimensionality, it is challenging to both extract surrogate models at the low level of the design hierarchy and to handle them in the high-level simulation. In this paper, we develop an efficient analysis of variance-based stochastic circuit/microelectromechanical systems simulator to efficiently extract the surrogate models at the low level. In order to avoid the curse of dimensionality, we employ tensor-train decomposition at the high level to construct the basis functions and Gauss quadrature points. As a demonstration, we verify our algorithm on a stochastic oscillator with four MEMS capacitors and 184 random parameters. This challenging example is efficiently simulated by our simulator at the cost of only 10min in MATLAB on a regular personal computer. Analysis and Design of Weakly Coupled LC Oscillator Arrays Based on Phase-Domain Macromodels Maffezzoni, P. ; Bahr, B. ; Zhang, Z. ; Daniel, L. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6936872 An array of weakly coupled oscillators can generate multiphase signals, i.e., multiple sinusoidal signals with specific phase separations. Multiphase oscillators are attractive solutions in many electronic applications such as the synchronization of multiple processing units in digital electronics and the frequency synthesis in mixed-signal radio frequency circuits. Due to the complexity of multiphase oscillators and the large number of design parameters, novel simulation techniques are highly desired to efficiently handle such large-scale problems. In this paper, an efficient phase-domain simulation technique is proposed to calculate the phase response of inductance capacitance oscillator array. By some practical examples, it is shown how the proposed method can be exploited to identify the array topologies and parameter settings that guarantee stable phase separations. It is also shown how the proposed technique can be used to evaluate phase-noise performance. Formulation of the Obreshkov-Based Transient Circuit Simulator in the Presence of Nonlinear Memory Elements Lin, Y. ; Gad, E. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6935006 The high-order $A$ - and $L$ -stable Obreshkov-based method was recently proposed for simulating the transient response of general nonlinear circuits in the time-domain. This method has consistently resulted in more than one order-of-magnitude speedup compared with the traditional methods used in the SPICE engine. Nonetheless, the formulation of this Obreshkov-based approach assumed that the memory elements in the circuits are characterized by a linear constituent equation. The goal of this paper is to generalize this approach to handle memory elements that are described by nonlinear constituent equations. PHYSICAL DESIGN A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding Su, H. ; Chen, C. ; Li, Y. ; Tu, A. ; WU, C. ; Huang, C. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6948322 As design-for-manufacturability techniques have become widely used to improve the yield of nano-scale semiconductor technology in recent years, hotspot detection methods have been investigated with a view to calibrating layout patterns that tend to reduce yield. In this paper, we propose two graph models, i.e., skeleton graph and space graph, to formulate polygon topology and spatial relationship among polygons. In addition, a Prüfer encoding-based method is presented to encode each skeleton graph. Single polygon matching problem is then equivalent to the verification of graph isomorphism, which is realized by checking the identity of two enhanced Prüfer codes associated with two skeleton graphs. A branch and bound-based pattern anchoring algorithm is presented to resolve the vertex ordering problem for isomorphism checking. The general exact pattern matching problem can then be accomplished by adopting the space graph to identify the similarity of spatial relationship among polygons. Vias are one of the most device components that attract much attention in monitoring manufacturing variation due to via alignment issue, but hotspot detection rarely takes vias into consideration. Multilayer hotspot detection can also be realized by extending the skeleton graph to maintain the relations between adjacent layers through vias. Experimental results show that we can achieve $5.6times $ runtime speedup than design-rule-based methodology in average for single layer hotspot detection while the runtime for multilayer hotspot is roughly equal to the summation of that for individual single layer hotspot detection. SYSTEM-LEVEL DESIGN Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor Wang, X. ; Winemberg, L. ; Su, D. ; Tran, D. ; George, S. ; Ahmed, N. ; Palosh, S. ; Dobin, A. ; Tehranipoor, M. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6948227 As process technology further scales, aging, noise and variations in integrated circuits (ICs) and systems become a major challenge to both the semiconductor and electronic design automation (EDA) industries, which may cause significantly increased mismatch between modeled and actual silicon behavior, and even IC failure in field. Therefore, the addition of accurate and low-cost on-chip sensors is of great value to reduce the mismatch and perform in-field measurements. This paper presents a novel standard-cell-based sensor for reliability analysis of digital ICs (called Radic), in order to better understand the characteristics of gate, functional path aging and process variations’ impact on timing performance, and perform in-field aging measurements. The Radic sensor has been fabricated on two floating gate Freescale SoCs in very advanced technology. The measurement results demonstrate that the resolution can be better than 0.1 ps, and the accuracy is kept throughout aging/process variation. Additionally, a built-in aging adaption system based on Radic sensor is proposed to perform in-field aging adaption. Simulation results verify that, comparing with designs with fixed aging guardband, the proposed aging adaption system releases 80% of aging timing margin, saves silicon area by 1.02%–3.16% at most targeting frequencies, and prevents aging induced failure. TEST Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs Agrawal, M. ; Chakrabarty, K. ; Widialaksono, R. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6954482 Three-dimensional (3-D) stacking of integrated circuits (ICs) using through-silicon-vias (TSVs) is a promising integration platform for next-generation ICs. Since TSVs are not fully accessible prior to bonding, it is difficult to test the combinational logic between scan flip-flops and TSVs at a prebond stage. In order to increase testability, it has been advocated that wrapper cells (WC) be added at both ends of a TSV. However, a drawback of WC is that they incur area overhead and lead to higher latency and performance degradation on functional paths. Prior work proposed the reuse of scan cells to achieve high testability, thereby reducing the number of WC that need to be inserted; however, practical timing considerations were overlooked and the number of inserted WC was still high. We show that the general problem of minimizing the WC is equivalent to the graph-theoretic minimum clique-partitioning problem, and is therefore NP-hard. We adopt efficient heuristic methods to solve the problem and describe a timing-guided and layout-aware solution. We evaluate the heuristic methods using an exact solution technique based on integer linear programming. We also present design-for-test optimization technique to leverage the reuse-based method during post-bond testing. Results are presented for 3-D-stack implementations of the ITC’99 and the OpenCore benchmark circuits. Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs Wang, R. ; Chakrabarty, K. ; Bhawmik, S. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6936331 Interposer-based 2.5-D integrated circuits (ICs) are seen today as a first step toward the eventual industry adoption of 3-D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnect-test solution that targets TSVs, RDL wires, and micro-bumps for shorts, opens, and delay faults. The proposed test technique is fully compatible with the IEEE 1149.1 Standard. To reduce test cost, we also present a test-path design and scheduling technique that minimizes a composite cost function based on test time and the design-for-test overhead in terms of additional TSVs and micro-bumps needed for test access. The locations of the dies on the interposer are taken into consideration in order to determine the order of dies in a single test path. We present simulation results to demonstrate the effectiveness of fault detection, and synthesis results to evaluate the hardware cost per die relative to the IEEE 1149.1 Standard. We also present test-path design and test-scheduling results to highlight the effectiveness of the optimization technique. SHORT Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq Wang, Q. ; Song, X. ; Hung, W.N.N. ; Gu, M. ; Sun, J. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6926810 Theorem proving has been demonstrated as a powerful technique for datapath verification. This paper considers a generic logic-level architecture of end-around-carry adder, which is extensively used in floating-point arithmetic. The architecture is component-based and parameterized for easy customization. The design architecture is formalized and verified in the mechanical theorem prover Coq. The scalable proof provides necessary underpinnings for verifying customized and new implementations. SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis Xydis, S. ; Palermo, G. ; Zaccaria, V. ; Silvano, C. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6930749 Supervised high-level synthesis (HLS) is a new class of design problems where exploration strategies play the role of supervisor for tuning an HLS engine. The complexity of the problem is increased due to the large set of tunable parameters exposed by the “new wave” of HLS tools that include not only architectural alternatives but also compiler transformations. In this paper, we developed a novel exploration approach, called spectral-aware Pareto iterative refinement, that exploits response surface models (RSMs) and spectral analysis for predicting the quality of the design points without resorting to costly architectural synthesis procedures. We show that the target solution space can be accurately modeled through RSMs, thus enabling a speedup of the overall exploration without compromising the quality of results. Furthermore, we introduce the usage of spectral techniques to find high variance regions of the design space that require analysis for improving the RSMs prediction accuracy. 3 -------------------------------------------------------------------------------------------------------------------------------- DAC 2015 Designer Track Designers and software developers from Intel, IBM, Samsung, TI, Toshiba, Qualcomm, AMD, Freescale, and other leading IC companies will present their design experiences on effective design flows, methods, and tool usage. Designer Track will include presentations, a poster session and a rich set of invited talks. It offers a unique opportunity to network with and learn from other industry experts. There is no other way to improve your “design IQ” in such a short amount of time. Designer Track focuses on the hardware designers and embedded software developers, these attendees expertise complements DAC’s strong research focus on algorithms and methodology. The Designer Track aims to illustrate both benefits and challenges of design and software development, and provides educational and networking benefits for designers, software engineers and tool developers. The covered topics are at the interface between design and automation, an area that until now has been under-represented in EDA. The Designer Track is intended specifically for practitioners. Whether you are an EDA tool user, hardware designer, software engineer, application engineer or a consultant, the Designer Track is an ideal place to meet and share your experiences. SUBMISSION REQUIREMENTS * Title of the presentation * Abstract of 100 words maximum * Category (list below) * Organizer(s) name, affiliation, city, state, country, and email address * Presenter(s) name, affiliation, city, state, country, and email address * Upload 6 slides maximum, PowerPoint presentation Submission Closes January 20, 2015 More information at: https://dac.com/submission-categories/designer-track-submissions ------------------ YOU HAVE RECEIVED THIS E-MAIL BECAUSE YOU ARE SUBSCRIBED TO THE IEEE CEDA MAILING LIST. IF YOU WANT TO BE UNSUBSCRIBED FROM THIS LIST, PLEASE SEND AN EMPTY E-MAIL FROM YOUR E-MAIL ACCOUNT TO: ceda-unsubscr...@listes.epfl.ch -- -- ==================================================================== Jose L. Ayala, PhD E-Mail: jay...@ucm.es Computer Science Faculty Phone: (+34) 91 3947614 Complutense University of Madrid Fax: (+34) 91 3947527 C/ Prof. José García Santesmases, s/n www.dacya.ucm.es/jlayala 28040 Madrid, Spain ====================================================================
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