Signed-off-by: Troy Kisky <troy.ki...@boundarydevices.com> --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 56 ++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 8 deletions(-)
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 2af4265..3a1f1bc 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -56,7 +56,6 @@ IOMUX_ENTRY1(IOM_DRAM_SDQS0, 0x00000030) IOMUX_ENTRY1(IOM_DRAM_SDQS1, 0x00000030) IOMUX_ENTRY1(IOM_DRAM_SDQS2, 0x00000030) IOMUX_ENTRY1(IOM_DRAM_SDQS3, 0x00000030) - IOMUX_ENTRY1(IOM_DRAM_SDQS4, 0x00000030) IOMUX_ENTRY1(IOM_DRAM_SDQS5, 0x00000030) IOMUX_ENTRY1(IOM_DRAM_SDQS6, 0x00000030) @@ -66,7 +65,6 @@ IOMUX_ENTRY1(IOM_DRAM_DQM0, 0x00020030) IOMUX_ENTRY1(IOM_DRAM_DQM1, 0x00020030) IOMUX_ENTRY1(IOM_DRAM_DQM2, 0x00020030) IOMUX_ENTRY1(IOM_DRAM_DQM3, 0x00020030) - IOMUX_ENTRY1(IOM_DRAM_DQM4, 0x00020030) IOMUX_ENTRY1(IOM_DRAM_DQM5, 0x00020030) IOMUX_ENTRY1(IOM_DRAM_DQM6, 0x00020030) @@ -84,67 +82,108 @@ IOMUX_ENTRY1(IOM_DRAM_SDBA2, 0x00000000) IOMUX_ENTRY1(IOM_DRAM_SDODT0, 0x00003030) IOMUX_ENTRY1(IOM_DRAM_SDODT1, 0x00003030) + IOMUX_ENTRY1(IOM_GRP_B0DS, 0x00000030) IOMUX_ENTRY1(IOM_GRP_B1DS, 0x00000030) - IOMUX_ENTRY1(IOM_GRP_B2DS, 0x00000030) IOMUX_ENTRY1(IOM_GRP_B3DS, 0x00000030) IOMUX_ENTRY1(IOM_GRP_B4DS, 0x00000030) IOMUX_ENTRY1(IOM_GRP_B5DS, 0x00000030) - IOMUX_ENTRY1(IOM_GRP_B6DS, 0x00000030) IOMUX_ENTRY1(IOM_GRP_B7DS, 0x00000030) + IOMUX_ENTRY1(IOM_GRP_ADDDS, 0x00000030) +/* (differential input) */ IOMUX_ENTRY1(IOM_DDRMODE_CTL, 0x00020000) - +/* disable ddr pullups */ IOMUX_ENTRY1(IOM_GRP_DDRPKE, 0x00000000) +/* (differential input) */ IOMUX_ENTRY1(IOM_GRP_DDRMODE, 0x00020000) +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ IOMUX_ENTRY1(IOM_GRP_CTLDS, 0x00000030) IOMUX_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000) +/* Read data DQ Byte0-3 delay */ WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY0DL, 0x33333333) WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY1DL, 0x33333333) WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY2DL, 0x33333333) WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY3DL, 0x33333333) - WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333) WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333) WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333) WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333) + /* MDPDC - CKE pulse width = 3 cycles. CKSRE = 6 cycles, CKSRX = 6 cycles */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00020036) +/* + * MDMISC, mirroring, interleaved (row/bank/col) + */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740) +/* + * MDSCR, con_req + */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000) +/* + * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks + * tXP=4 clocks, tXPDLL=13 clocks + * tFAW=24 clocks, cas=8 cycles + */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG0, 0x555A7975) +/* + * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8 + * tMRD=4, tCWL=6 + */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64) +/* + * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4 + */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB) WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2) WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21) WRITE_ENTRY1(MMDC_P0 + MMDC_MDOTC, 0x09444040) WRITE_ENTRY1(MMDC_P0 + MMDC_MDPDC, 0x00025576) + +/* + * Mx6Q - 64 bit wide ddr + * last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) = + * 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27 + */ +/* MDASP, CS0_END */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDASP, 0x00000027) +/* + * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit + * mx6q : row+col+bank+width=14+10+3+3=30 = 1G + */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDCTL, 0x831A0000) +/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04088032) WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0408803A) +/* LOAD MR3, CS0 */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033) WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x0000803B) +/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428031) WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00428039) +/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408030) WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x09408038) +/* ZQ calibrate, CS0 */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040) WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008048) WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1380003) WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1380003) + +/* MDREF, 32KHz refresh, 4 refeshes each */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800) WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227) WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227) +/* MPDGCTRL0/1 DQS GATE*/ WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350) WRITE_ENTRY1(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359) WRITE_ENTRY1(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350) @@ -153,17 +192,18 @@ WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B) WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341) WRITE_ENTRY1(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933) WRITE_ENTRY1(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36) - WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F) WRITE_ENTRY1(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F) - WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044) WRITE_ENTRY1(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044) +/* MPMUR0 - Complete calibration by forced measurement */ WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800) WRITE_ENTRY1(MMDC_P1 + MMDC_MPMUR0, 0x00000800) +/* MDSCR, enable ddr */ WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00000000) +/* MAPSR, 1024 cycles idle before self-refresh */ WRITE_ENTRY1(MMDC_P0 + MMDC_MAPSR, 0x00011006) /* set the default clock gate to save power */ -- 1.7.9.5 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
