Fabio,

On Tuesday, September 18, 2012 5:24:57 AM, Fabio Estevam wrote:
> Hi Benoît ,
> 
> On Mon, Sep 17, 2012 at 4:04 PM, Benoît Thébaudeau
> <benoit.thebaud...@advansee.com> wrote:
> 
> > +u32 get_board_rev(void)
> > +{
> > +       return get_cpu_rev();
> > +}
> 
> Is this enough?  Looking at FSL U-boot there is also a:
> 
> static inline void set_board_rev(void)
> {
>       if ((__REG(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
>               system_rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
> 
> }

I have a question regarding this code: Is it normal that it does not enable a
weak pull-up (100 k) on UART3_RXD's pad? According to the schematic history, the
pull-down R6001 (10 k) has been added to UART3_RXD for revision 2. By default,
the pad of this pin has its keeper enabled, not its pull, so everything is fine
with this code for revision 2, but what about revision 1?

To reformulate my question: Was there anything on this board before R6001
inputting a high level on UART3_RXD, or does the pad keeper guarantee some
default init level by design if the pin is externally left floating?

Best regards,
Benoît
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