On 05/23/2012 12:56 AM, Manukumar wrote: > > u-boot version: u-boot-2010.12 > > My OR and BR register values(according to our memory map): > BR0 0xFF800C21 OR0 0xFF800396 > BR1 0xE8000801 OR1 0xFFFF8074 > BR2 0xE8009001 OR2 0xFFFF8074 > > after defining VERBOSE_DEBUG in drivers/mtd/nand/fsl_elbc_nand.c > i gave sacveenv command, igot below logs. > please go through that and resolve asap.
People on this list are generally happy to help as time is available, but if you need "asap" either contact supp...@freescale.com (especially when using Freescale-supplied U-Boot) or another official Freescale FAE or support contact, or hire someone to look into it. > skipping bad block = > 0 I don't see this exact message in mainline U-Boot, even in old versions. And zero being a bad block would be a bad thing -- I suspect things have gone wrong before the output you provided. > DEBUG: set_addr: bank=0, ctrl->addr=0xff800000 (0xff800000), index 0, > pes 14 ps 9 > fsl_elbc_run_command > > DEBUG: fsl_elbc_run_command: fmr=0000f023 fir=4e000000 > fcr=70000000 > DEBUG: fsl_elbc_run_command: fbar=00000000 fpar=00000000 fbcr=00000001 > bank=0 > DEBUG: fsl_elbc_run_command: stat=40000001 mdr=00000000 > fmr=0000f020 This is showing a command timeout (LTESR[FCT]). What happened with the NAND earlier in the boot sequence? -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
