On Tuesday, December 20, 2011 01:06:07 PM you wrote: > Dear Andreas, > > In message <201112201253.46991.schnitzelt...@gmx.de> you wrote: > > I agree to your concerns but - as I understood Steve Sakoman - here the > > > situation is slightly different: > I think you misunderstand. Yes I think too :-) > > > At elder overo boards TWL4030 RTC irq is connected to gpio112. > > Unfortunately this pin is also used for binary revision detection. > > Therefore we need to send 'shut-up' to TWL4030 via i2c to avoid reading > > wrong revision. In SPL this must be done *before* SDRAM (timing) is set > > up, because the type of SDRAM is revision dependent. > > My suggestion was to check if memory initialization can not rather be > done _without_ reading (and without otherwise knowing) the board type > or revision. Usually this is possible, and I always prefer such > auto-adjusting solutions over hard-wired approaches that break down > when any of the expected inout data is not correct or not available. > Dear Wolfgang,
I don't know if I want to jump also into these changes now - especially since I am quite new here.. But for my intererst - since it seems more error tolerant: How is SDRAM timing set up without exactly knowing what type is connected? Is there a good example implementation in u-boot(-spl)? Best regards Andreas _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
