Dear "Moffett, Kyle D",
In message <fea1ab06-a66f-4180-a2b3-076e7c719...@boeing.com> you wrote:
>
> The correct E1000_WRITE_FLUSH macro should be:
> #define E1000_WRITE_FLUSH(a) \
> do { uint32_t x =3D E1000_READ_REG(a, STATUS); (void)x; } while(0=
> )
>
> It shouldn't return a value, it's just ensuring that writes are properly
> posted to the PCI bus.
Really? Should that not be guaranteed by the memory barriers inside
the E1000_READ_REG() code?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
"Here's a fish hangs in the net like a poor man's right in the law.
'Twill hardly come out." - Shakespeare, Pericles, Act II, Scene 1
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