From: Jerry Huang <chang-ming.hu...@freescale.com>
The new MPC8360EMDS board changes the oscillator to 33.33MHz in order to
support QE 500MHZ and this new board supports 512MB DDR since 2008,
but the u-boot only supports 256MB DDR and 66.6MHz oscillator on top tree,
For 512MB DDR:
BAT0 is used for the first 256MB memory, BAT4 is used for the second
256MB memory and the address space of SDRAM follows the DDR, so if the size
of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of DDR
is 512MB, the BAT4 will be used for the second 256MB memory and there is no BAT
for SDRAM.
Therefore, if the size of DDR is 512MB, this patch will use BAT6 for SDRAM
and BAT5 will be used for PCI MEM to replace the BAT6 after the codes relocates
to the DDR.
Signed-off-by: Jerry Huang <chang-ming.hu...@freescale.com>
---
cahnges for v2:
- fix multiline comment wrong
changes for v3:
- change the oscillator to 33330000, not 33300000
changes for v4:
- add the mandatory history of changes
changes for v5:
- move the code to platform file from lib/board.c
- add 2011 copyright
board/freescale/mpc8360emds/mpc8360emds.c | 36 ++++++++++++++++++++++++++++-
include/configs/MPC8360EMDS.h | 13 +++++-----
2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index 0babd26..7906f5e 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
* Dave Liu <dave...@freescale.com>
*
* See file CREDITS for list of people who contributed to this
@@ -23,6 +23,7 @@
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
+#include <asm/mmu.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
@@ -138,9 +139,26 @@ int board_early_init_f(void)
int board_early_init_r(void)
{
+ gd_t *gd;
#ifdef CONFIG_PQ_MDS_PIB
pib_init();
#endif
+ /*
+ * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
+ * So re-setup PCI MEM space used BAT5 after relocated to DDR
+ */
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+ if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+ /* Clear the BAT5 */
+ write_bat(DBAT5, 0, 0);
+ write_bat(IBAT5, 0, 0);
+ asm("sync");
+ /* Setup BAT5 for PCI MEM */
+ write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
+ write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
+ asm("sync");
+ }
+
return 0;
}
@@ -290,6 +308,22 @@ static int sdram_init(unsigned int base)
if (rem)
base = base - rem + sdram_size;
+ /*
+ * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
+ * After relocated to DDR, re-setup PCI MEM space used BAT5
+ */
+ if (base > CONFIG_MAX_MEM_MAPPED) {
+ unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
+ unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
+
+ write_bat(DBAT6, 0, 0); /* Clear the BAT6 */
+ write_bat(IBAT6, 0, 0);
+ asm("sync");
+ write_bat(DBAT6, batu, batl); /* Setup the BAT6 for SDRAM */
+ write_bat(IBAT6, batu, batl);
+ asm("sync");
+ }
+
sdram_addr = (uint *)base;
/*
* Setup SDRAM Base and Option Registers
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index a959940..00ea85a 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
*
* Dave Liu <dave...@freescale.com>
*
@@ -40,13 +40,13 @@
* System Clock Setup
*/
#ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
+#define CONFIG_83XX_PCICLK 33330000 /* in HZ */
#else
-#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
+#define CONFIG_83XX_CLKIN 33330000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ 66000000
+#define CONFIG_SYS_CLK_FREQ 33330000
#endif
/*
@@ -55,11 +55,11 @@
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
+ HRCWL_CSB_TO_CLKIN_8X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CE_PLL_VCO_DIV_4 |\
HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X6 |\
+ HRCWL_CE_TO_PLL_1X15 |\
HRCWL_CORE_TO_CSB_2X1)
#ifdef CONFIG_PCISLAVE
@@ -506,6 +506,7 @@
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+#define CONFIG_BAT_RW
/* DDR/LBC SDRAM: cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 |
BATL_MEMCOHERENCE)
--
1.6.4
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