[PATCH 8/9] clk: mediatek: mt7988: convert to mtk_gate_clk_data

[Julien Stephan]

MT7988 currently declares a separate U_BOOT_DRIVER, probe() function
and compatible table for each clock gate controller, despite all of
them sharing the same implementation.

Convert MT7988 to use the generic mtk_gate_clk_data infrastructure.
sgmiisys_0 and sgmiisys_1 are merged into a single generic driver,
while ethdma and ethwarp keep their own U_BOOT_DRIVERs since they
bind different reset controllers, but share the generic probe()
function.

No functional change intended.

Signed-off-by: Julien Stephan <jstep...@baylibre.com>
---
 drivers/clk/mediatek/clk-mt7988.c | 74 +++++++++++++++------------------------
 1 file changed, 28 insertions(+), 46 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt7988.c 
b/drivers/clk/mediatek/clk-mt7988.c
index ebad78a9151..90bed15b4c7 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -933,10 +933,15 @@ static const struct mtk_gate ethdma_mtk_gate[] = {
        GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
 };
 
-static int mt7988_ethdma_probe(struct udevice *dev)
+static int mt7988_clk_gate_probe(struct udevice *dev)
 {
-       return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, ethdma_mtk_gate,
-                                       ARRAY_SIZE(ethdma_mtk_gate), 0);
+       struct mtk_gate_clk_data *data;
+
+       data = (void *)dev_get_driver_data(dev);
+
+       return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
+                                       data->gates, data->num_gates,
+                                       data->gates[0].id);
 }
 
 static int mt7988_ethdma_bind(struct udevice *dev)
@@ -952,9 +957,12 @@ static int mt7988_ethdma_bind(struct udevice *dev)
        return ret;
 }
 
+MTK_GATE_CLK_DATA(ethdma_mtk_gate);
+
 static const struct udevice_id mt7988_ethdma_compat[] = {
        {
                .compatible = "mediatek,mt7988-ethdma",
+               .data = (ulong)&ethdma_mtk_gate_data,
        },
        {}
 };
@@ -963,7 +971,7 @@ U_BOOT_DRIVER(mt7988_clk_ethdma) = {
        .name = "mt7988-clock-ethdma",
        .id = UCLASS_CLK,
        .of_match = mt7988_ethdma_compat,
-       .probe = mt7988_ethdma_probe,
+       .probe = mt7988_clk_gate_probe,
        .bind = mt7988_ethdma_bind,
        .priv_auto = sizeof(struct mtk_cg_priv),
        .ops = &mtk_clk_gate_ops,
@@ -991,29 +999,6 @@ static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
        GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3),
 };
 
-static int mt7988_sgmiisys_0_probe(struct udevice *dev)
-{
-       return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-                                       sgmiisys_0_mtk_gate,
-                                       ARRAY_SIZE(sgmiisys_0_mtk_gate), 0);
-}
-
-static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
-       {
-               .compatible = "mediatek,mt7988-sgmiisys_0",
-       },
-       {}
-};
-
-U_BOOT_DRIVER(mt7988_clk_sgmiisys_0) = {
-       .name = "mt7988-clock-sgmiisys_0",
-       .id = UCLASS_CLK,
-       .of_match = mt7988_sgmiisys_0_compat,
-       .probe = mt7988_sgmiisys_0_probe,
-       .priv_auto = sizeof(struct mtk_cg_priv),
-       .ops = &mtk_clk_gate_ops,
-};
-
 /* SGMIISYS_1 */
 
 static const struct mtk_gate_regs sgmii1_cg_regs = {
@@ -1036,25 +1021,26 @@ static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
        GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3),
 };
 
-static int mt7988_sgmiisys_1_probe(struct udevice *dev)
-{
-       return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-                                       sgmiisys_1_mtk_gate,
-                                       ARRAY_SIZE(sgmiisys_1_mtk_gate), 0);
-}
+MTK_GATE_CLK_DATA(sgmiisys_0_mtk_gate);
+MTK_GATE_CLK_DATA(sgmiisys_1_mtk_gate);
 
-static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
+static const struct udevice_id mt7988_clk_gate_compat[] = {
+       {
+               .compatible = "mediatek,mt7988-sgmiisys_0",
+               .data = (ulong)&sgmiisys_0_mtk_gate_data,
+       },
        {
                .compatible = "mediatek,mt7988-sgmiisys_1",
+               .data = (ulong)&sgmiisys_1_mtk_gate_data,
        },
        {}
 };
 
-U_BOOT_DRIVER(mt7988_clk_sgmiisys_1) = {
-       .name = "mt7988-clock-sgmiisys_1",
+U_BOOT_DRIVER(mt7988_clk_gate) = {
+       .name = "mt7988-gate-clk",
        .id = UCLASS_CLK,
-       .of_match = mt7988_sgmiisys_1_compat,
-       .probe = mt7988_sgmiisys_1_probe,
+       .of_match = mt7988_clk_gate_compat,
+       .probe = mt7988_clk_gate_probe,
        .priv_auto = sizeof(struct mtk_cg_priv),
        .ops = &mtk_clk_gate_ops,
 };
@@ -1083,13 +1069,6 @@ static const struct mtk_gate ethwarp_mtk_gate[] = {
                     CLK_TOP_NETSYS_MCU_SEL, 15),
 };
 
-static int mt7988_ethwarp_probe(struct udevice *dev)
-{
-       return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-                                       ethwarp_mtk_gate,
-                                       ARRAY_SIZE(ethwarp_mtk_gate), 0);
-}
-
 static int mt7988_ethwarp_bind(struct udevice *dev)
 {
        int ret = 0;
@@ -1103,9 +1082,12 @@ static int mt7988_ethwarp_bind(struct udevice *dev)
        return ret;
 }
 
+MTK_GATE_CLK_DATA(ethwarp_mtk_gate);
+
 static const struct udevice_id mt7988_ethwarp_compat[] = {
        {
                .compatible = "mediatek,mt7988-ethwarp",
+               .data = (ulong)&ethwarp_mtk_gate_data,
        },
        {}
 };
@@ -1114,7 +1096,7 @@ U_BOOT_DRIVER(mt7988_clk_ethwarp) = {
        .name = "mt7988-clock-ethwarp",
        .id = UCLASS_CLK,
        .of_match = mt7988_ethwarp_compat,
-       .probe = mt7988_ethwarp_probe,
+       .probe = mt7988_clk_gate_probe,
        .bind = mt7988_ethwarp_bind,
        .priv_auto = sizeof(struct mtk_cg_priv),
        .ops = &mtk_clk_gate_ops,

-- 
2.54.0