MT7623 currently declares a separate U_BOOT_DRIVER and probe() function for each clock gate controller, despite all of them sharing the same implementation.
Convert MT7623 to use the generic mtk_gate_clk_data infrastructure so that all clock gate controllers share a single probe() function. The infracfg controller keeps its own U_BOOT_DRIVER since it is the only one bound before relocation (DM_FLAG_PRE_RELOC), while ethsys and hifsys, which both bind the same reset controller, are merged into a single driver. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> --- drivers/clk/mediatek/clk-mt7623.c | 67 ++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 37 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 56912ebdb53..84fe68dd925 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -1069,10 +1069,15 @@ static const struct mtk_clk_tree mt7623_clk_gate_tree = { .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; -static int mt7623_infracfg_probe(struct udevice *dev) +static int mt7623_clk_gate_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, infra_cgs, - ARRAY_SIZE(infra_cgs), 1); + struct mtk_gate_clk_data *data; + + data = (void *)dev_get_driver_data(dev); + + return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, + data->gates, data->num_gates, + data->gates[0].id); } static const struct mtk_clk_tree mt7623_clk_peri_tree = { @@ -1093,18 +1098,6 @@ static int mt7623_pericfg_probe(struct udevice *dev) return mtk_common_clk_init(dev, &mt7623_clk_peri_tree); } -static int mt7623_hifsys_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, hif_cgs, - ARRAY_SIZE(hif_cgs), 1); -} - -static int mt7623_ethsys_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, eth_cgs, - ARRAY_SIZE(eth_cgs), 1); -} - static int mt7623_ethsys_hifsys_bind(struct udevice *dev) { int ret = 0; @@ -1128,8 +1121,13 @@ static const struct udevice_id mt7623_topckgen_compat[] = { { } }; +MTK_GATE_CLK_DATA(infra_cgs); + static const struct udevice_id mt7623_infracfg_compat[] = { - { .compatible = "mediatek,mt7623-infracfg", }, + { + .compatible = "mediatek,mt7623-infracfg", + .data = (ulong)&infra_cgs_data + }, { } }; @@ -1138,13 +1136,18 @@ static const struct udevice_id mt7623_pericfg_compat[] = { { } }; -static const struct udevice_id mt7623_ethsys_compat[] = { - { .compatible = "mediatek,mt7623-ethsys" }, - { } -}; +MTK_GATE_CLK_DATA(hif_cgs); +MTK_GATE_CLK_DATA(eth_cgs); -static const struct udevice_id mt7623_hifsys_compat[] = { - { .compatible = "mediatek,mt7623-hifsys" }, +static const struct udevice_id mt7623_clk_gate_reset_compat[] = { + { + .compatible = "mediatek,mt7623-ethsys", + .data = (ulong)ð_cgs_data + }, + { + .compatible = "mediatek,mt7623-hifsys", + .data = (ulong)&hif_cgs_data + }, { } }; @@ -1187,7 +1190,7 @@ U_BOOT_DRIVER(mt7623_clk_infracfg) = { .name = "mt7623-infracfg", .id = UCLASS_CLK, .of_match = mt7623_infracfg_compat, - .probe = mt7623_infracfg_probe, + .probe = mt7623_clk_gate_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, .flags = DM_FLAG_PRE_RELOC, @@ -1203,21 +1206,11 @@ U_BOOT_DRIVER(mt7623_clk_pericfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mt7623_clk_hifsys) = { - .name = "mt7623-clock-hifsys", - .id = UCLASS_CLK, - .of_match = mt7623_hifsys_compat, - .probe = mt7623_hifsys_probe, - .bind = mt7623_ethsys_hifsys_bind, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, -}; - -U_BOOT_DRIVER(mt7623_clk_ethsys) = { - .name = "mt7623-clock-ethsys", +U_BOOT_DRIVER(mt7623_clk_gate_reset) = { + .name = "mt7623-gate-clk-reset", .id = UCLASS_CLK, - .of_match = mt7623_ethsys_compat, - .probe = mt7623_ethsys_probe, + .of_match = mt7623_clk_gate_reset_compat, + .probe = mt7623_clk_gate_probe, .bind = mt7623_ethsys_hifsys_bind, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, -- 2.54.0
