> BTW T.F. I want to point out a very important setup. > By default the Altera trunk had turned on > > │ │ [*] Enable U-Boot watchdog reset > │ │ > │ │ [*] Automatically start watchdog timer > │ │ > │ │ (10000) Watchdog timeout in msec > │ │ > │ │ [ ] Enable Watchdog Timer support for IMX and LSCH2 of NXP > │ │ > │ │ [ ] i.MX7ULP watchdog > │ │ > │ │ -*- Designware watchdog timer support > │ │ > │ │ [*] Enable driver model for watchdog timer drivers > > So maybe you can also reverse investigate on your side via real board. > Removing all CYCLIC WDT drivers and all dst watchdog "okay" do > not introduce sdram calibration issue? > > Lets cross check.
Hi T.F. and adding Alif as well. Long story short it fails on Altera trunk as follow: 1: Altera trunk force enable the driver of DESIGNWARE_WATCHDOG 2: It is not allow to remove by default git pull 3: After manually remove via Kconfig modification config TARGET_SOCFPGA_GEN5 bool # select DESIGNWARE_WATCHDOG 4: The DESIGNWARE and all CYCLIC are turned off DTS, .config had double confirmed the setup Test result: U-Boot SPL 2025.07-g35abb4f1cedc-dirty (Nov 28 2025 - 20:19:39 +0800) SDRAM calibration failed. ### ERROR ### Please RESET the board ### Long story short the inherent patch for this series is actually correct. The WDT introduces calibration failures. Thanks, Brian
