Hi Brian,
On 28/11/2025 6:04 am, Sune Brian wrote:
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Hi all
CMD_CYCLIC is enabled by default ("default y") if its dependencies are
met (that is "CYCLIC" as specified by "depends on CYCLIC" in
cmd/Kconfig). So when you enable CONFIG_CYCLIC via menuconfig, it
enables (by default) CMD_CYCLIC as well. But you can disable it if you
don't need it for example. If you add a "select OPTION" in an option in
Kconfig, you cannot disable OPTION anymore.
CMD_CYCLIC is not required, so you shouldn't "depends on" or "select" it.
Yes this patch had removed it by cross-check via real board on the fail
calibration issue. But CYCLIC and CYCLIC_SPL still a must to fix the issue.
Brian
Would Altera also confirm this issue a bit?
I can repeat this issue by a fresh pull build.
Thanks for sharing your findings. However, based on the behavior you
described, I’m not fully convinced that enabling cyclic/watchdog is
actually fixing the SDRAM calibration issue itself. From the SPL side,
there is no clear timeout or calibration control path that would
logically be corrected by turning on the cyclic framework, so the
improvement may simply be due to timing shifts rather than a real fix.
Before we go deeper into upstream work, could you try testing against
the official Altera downstream tree?
Altera official U-Boot (SoCFPGA):
https://github.com/altera-fpga/u-boot-socfpga - branch socfpga_v2025.07
This branch includes several Gen5 DDR related fixes that are not
upstreamed yet. If calibration becomes stable with the downstream tree,
then it is very likely that the real fix already exists there, and we
can identify which patch addresses the root cause instead of spending
time reverse engineering a solution that may already be solved.
If the calibration still fails even on the official release, then at
least we can rule out downstream fixes and focus efforts on the correct
upstream location.
Let me know the results, it will help us pinpoint whether the issue is
timing-related or missing a specific patch.
Thanks.
Tien Fong
