Adding iMX95/iMX94 support to the dw driver. Follow kernel driver
stype to use flags to distinguish the characteristic of different
platforms.
Signed-off-by: Ye Li <ye...@nxp.com>
---
drivers/pci/Kconfig | 2 +-
drivers/pci/pcie_dw_imx.c | 420 +++++++++++++++++++++++++++++++++++++++++-----
2 files changed, 377 insertions(+), 45 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 8ffd88c722d9..9ec3ed856bfb 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -456,7 +456,7 @@ config PCIE_STARFIVE_JH7110
config PCIE_DW_IMX
bool "i.MX DW PCIe controller support"
- depends on ARCH_IMX8M
+ depends on ARCH_IMX8M || ARCH_IMX9
select PCIE_DW_COMMON
select DM_REGULATOR
select REGMAP
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
index fdb463710ba1..f84c7180560a 100644
--- a/drivers/pci/pcie_dw_imx.c
+++ b/drivers/pci/pcie_dw_imx.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024 Linaro Ltd.
+ * Copyright 2025 NXP
*
* Author: Sumit Garg <sumit.g...@linaro.org>
*/
@@ -45,6 +46,47 @@
#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+#define IMX95_PCIE_PHY_GEN_CTRL 0x0
+#define IMX95_PCIE_REF_USE_PAD BIT(17)
+
+#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10
+#define IMX95_PCIE_PHY_MPLL_STATE BIT(30)
+
+#define IMX95_PCIE_SS_RW_REG_0 0xf0
+#define IMX95_PCIE_REF_CLKEN BIT(23)
+#define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
+#define IMX95_PCIE_SS_RW_REG_1 0xf4
+#define IMX95_PCIE_CLKREQ_OVERRIDE_EN BIT(8)
+#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL BIT(9)
+#define IMX95_PCIE_SYS_AUX_PWR_DET BIT(31)
+
+#define IMX95_PE0_GEN_CTRL_1 0x1050
+#define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0)
+
+#define IMX95_PE0_GEN_CTRL_3 0x1058
+#define IMX95_PCIE_LTSSM_EN BIT(0)
+
+#define IMX95_PCIE_RST_CTRL 0x3010
+#define IMX95_PCIE_COLD_RST BIT(0)
+
+#define GEN3_RELATED_OFF 0x890
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1
+
+#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3)
+#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4)
+#define IMX_PCIE_FLAG_HAS_SERDES BIT(6)
+
+#define IMX_PCIE_MAX_INSTANCES 2
+
+/* Parameters for the waiting for PCIe PHY PLL to lock s*/
+#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
+#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX /
1000)
+
struct pcie_dw_imx {
/* Must be first member of the struct */
struct pcie_dw dw;
@@ -54,20 +96,203 @@ struct pcie_dw_imx {
struct reset_ctl apps_reset;
struct phy phy;
struct udevice *vpcie;
+ void *info;
+ u32 max_link_speed;
+ bool enable_ext_refclk;
+ bool supports_clkreq;
};
struct pcie_chip_info {
+ u32 flags;
+ const u32 ltssm_off;
+ const u32 ltssm_mask;
+ const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
+ const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
const char *gpr;
+ void (*init_phy)(struct pcie_dw_imx *priv);
+ int (*enable_ref_clk)(struct pcie_dw_imx *priv, bool enable);
+ int (*core_reset)(struct pcie_dw_imx *priv, bool assert);
+ int (*wait_pll_lock)(struct pcie_dw_imx *priv);
+ void (*post_config)(struct pcie_dw_imx *priv);
};
+static void imx95_pcie_init_phy(struct pcie_dw_imx *priv)
+{
+/*
+ * Workaround for ERR051624: The Controller Without Vaux Cannot
+ * Exit L23 Ready Through Beacon or PERST# De-assertion
+ *
+ * When the auxiliary power is not available the controller
+ * cannot exit from L23 Ready with beacon or PERST# de-assertion
+ * when main power is not removed.
+ *
+ * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
+ */
+ regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
+ IMX95_PCIE_SYS_AUX_PWR_DET, IMX95_PCIE_SYS_AUX_PWR_DET);
+
+ regmap_update_bits(priv->iomuxc_gpr,
+ IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_PHY_CR_PARA_SEL,
+ IMX95_PCIE_PHY_CR_PARA_SEL);
+
+ if (priv->enable_ext_refclk) {
+ /* External clock is used as reference clock */
+ regmap_update_bits(priv->iomuxc_gpr,
+ IMX95_PCIE_PHY_GEN_CTRL,
+ IMX95_PCIE_REF_USE_PAD,
+ IMX95_PCIE_REF_USE_PAD);
+ regmap_update_bits(priv->iomuxc_gpr,
+ IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_REF_CLKEN, 0);
+ } else {
+ regmap_update_bits(priv->iomuxc_gpr,
+ IMX95_PCIE_PHY_GEN_CTRL,
+ IMX95_PCIE_REF_USE_PAD, 0);
+
+ regmap_update_bits(priv->iomuxc_gpr,
+ IMX95_PCIE_SS_RW_REG_0,
+ IMX95_PCIE_REF_CLKEN,
+ IMX95_PCIE_REF_CLKEN);
+ }
+
+ /* Force CLKREQ# low by override */
+ if (!priv->supports_clkreq)
+ regmap_update_bits(priv->iomuxc_gpr,
+ IMX95_PCIE_SS_RW_REG_1,
+ IMX95_PCIE_CLKREQ_OVERRIDE_EN |
+ IMX95_PCIE_CLKREQ_OVERRIDE_VAL,
+ IMX95_PCIE_CLKREQ_OVERRIDE_EN |
+ IMX95_PCIE_CLKREQ_OVERRIDE_VAL);
+}
+
+static int imx95_pcie_wait_for_phy_pll_lock(struct pcie_dw_imx *priv)
+{
+ u32 val;
+
+ if (regmap_read_poll_timeout(priv->iomuxc_gpr,
+ IMX95_PCIE_PHY_MPLLA_CTRL, val,
+ val & IMX95_PCIE_PHY_MPLL_STATE,
+ PHY_PLL_LOCK_WAIT_USLEEP_MAX,
+ PHY_PLL_LOCK_WAIT_TIMEOUT)) {
+ printf("PCIe PLL lock timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int imx95_pcie_core_reset(struct pcie_dw_imx *priv, bool assert)
+{
+ u32 val;
+
+ if (assert) {
+ /*
+ * From i.MX95 PCIe PHY perspective, the COLD reset toggle
+ * should be complete after power-up by the following sequence.
+ * > 10us(at power-up)
+ * > 10ns(warm reset)
+ * |<------------>|
+ * ______________
+ * phy_reset ____/ \________________
+ * ____________
+ * ref_clk_en_______________________/
+ * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
+ */
+ regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+ IMX95_PCIE_COLD_RST, IMX95_PCIE_COLD_RST);
+ /*
+ * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
+ * hardware by doing a read. Otherwise, there is no guarantee
+ * that the write has reached the hardware before udelay().
+ */
+ regmap_read(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+ &val);
+ udelay(15);
+ regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+ IMX95_PCIE_COLD_RST, 0);
+ regmap_read(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+ &val);
+ udelay(10);
+ }
+
+ return 0;
+}
+
+static void imx95_pcie_post_config(struct pcie_dw_imx *priv)
+{
+ u32 val;
+
+ /*
+ * Workaround for ERR051586: Compliance with 8GT/s Receiver
+ * Impedance ECN
+ *
+ * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] is
+ * 1 which makes receiver non-compliant with the ZRX-DC
+ * parameter for 2.5 GT/s when operating at 8 GT/s or higher. It
+ * causes unnecessary timeout in L1.
+ *
+ * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] to 0.
+ */
+ dw_pcie_dbi_write_enable(&priv->dw, true);
+ val = readl(priv->dw.dbi_base + GEN3_RELATED_OFF);
+ val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
+ writel(val, priv->dw.dbi_base + GEN3_RELATED_OFF);
+ dw_pcie_dbi_write_enable(&priv->dw, false);
+}
+
+static int imx8mm_pcie_enable_ref_clk(struct pcie_dw_imx *priv, bool enable)
+{
+ regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE,
+ enable ? 0 : IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE);
+ regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+ enable ? IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
+ return 0;
+}
+
static const struct pcie_chip_info imx8mm_chip_info = {
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET | IMX_PCIE_FLAG_HAS_PHYDRV,
.gpr = "fsl,imx8mm-iomuxc-gpr",
+ .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
};
static const struct pcie_chip_info imx8mp_chip_info = {
+ .flags = IMX_PCIE_FLAG_HAS_APP_RESET | IMX_PCIE_FLAG_HAS_PHYDRV,
.gpr = "fsl,imx8mp-iomuxc-gpr",
+ .enable_ref_clk = imx8mm_pcie_enable_ref_clk,
+};
+
+static const struct pcie_chip_info imx95_chip_info = {
+ .flags = IMX_PCIE_FLAG_HAS_SERDES,
+ .ltssm_off = IMX95_PE0_GEN_CTRL_3,
+ .ltssm_mask = IMX95_PCIE_LTSSM_EN,
+ .mode_off[0] = IMX95_PE0_GEN_CTRL_1,
+ .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+ .init_phy = imx95_pcie_init_phy,
+ .core_reset = imx95_pcie_core_reset,
+ .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
+ .post_config = imx95_pcie_post_config,
};
+static void imx_pcie_configure_type(struct pcie_dw_imx *priv)
+{
+ struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+ unsigned int mask, val, mode;
+
+ mode = PCI_EXP_TYPE_ROOT_PORT;
+
+ /* If mode_mask is 0, then generic PHY driver is used to set the mode */
+ if (!info->mode_mask[0])
+ return;
+
+ mask = info->mode_mask[0];
+ val = mode << (ffs(mask) - 1);
+
+ regmap_update_bits(priv->iomuxc_gpr, info->mode_off[0], mask, val);
+}
+
static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
{
dw_pcie_dbi_write_enable(&priv->dw, true);
@@ -75,17 +300,34 @@ static void pcie_dw_configure(struct pcie_dw_imx *priv,
u32 cap_speed)
clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY,
TARGET_LINK_SPEED_MASK, cap_speed);
+ clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CTL_2,
+ TARGET_LINK_SPEED_MASK, cap_speed);
+
dw_pcie_dbi_write_enable(&priv->dw, false);
}
static void imx_pcie_ltssm_enable(struct pcie_dw_imx *priv)
{
- reset_deassert(&priv->apps_reset);
+ struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+ if (info->ltssm_mask)
+ regmap_update_bits(priv->iomuxc_gpr, info->ltssm_off,
info->ltssm_mask,
+ info->ltssm_mask);
+
+ if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+ reset_deassert(&priv->apps_reset);
}
static void imx_pcie_ltssm_disable(struct pcie_dw_imx *priv)
{
- reset_assert(&priv->apps_reset);
+ struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+ if (info->ltssm_mask)
+ regmap_update_bits(priv->iomuxc_gpr, info->ltssm_off,
+ info->ltssm_mask, 0);
+
+ if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+ reset_assert(&priv->apps_reset);
}
static bool is_link_up(u32 val)
@@ -122,6 +364,11 @@ static int pcie_link_up(struct pcie_dw_imx *priv, u32
cap_speed)
static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv)
{
+ struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+ if (info->core_reset)
+ info->core_reset(priv, true);
+
if (dm_gpio_is_valid(&priv->reset_gpio)) {
dm_gpio_set_value(&priv->reset_gpio, 1);
mdelay(20);
@@ -133,6 +380,7 @@ static int imx_pcie_assert_core_reset(struct pcie_dw_imx
*priv)
static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
{
int ret;
+ struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
ret = clk_enable_bulk(&priv->clks);
if (ret)
@@ -142,11 +390,8 @@ static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
* Set the over ride low and enabled make sure that
* REF_CLK is turned on.
*/
- regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
- IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE, 0);
- regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
- IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
- IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
+ if (info->enable_ref_clk)
+ info->enable_ref_clk(priv, true);
/* allow the clocks to stabilize */
udelay(500);
@@ -156,6 +401,11 @@ static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
static void imx_pcie_deassert_core_reset(struct pcie_dw_imx *priv)
{
+ struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+ if (info->core_reset)
+ info->core_reset(priv, false);
+
if (!dm_gpio_is_valid(&priv->reset_gpio))
return;
@@ -170,10 +420,11 @@ static int pcie_dw_imx_probe(struct udevice *dev)
struct pcie_dw_imx *priv = dev_get_priv(dev);
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
int ret;
if (priv->vpcie) {
- ret = regulator_set_enable(priv->vpcie, true);
+ ret = regulator_set_enable_if_allowed(priv->vpcie, true);
if (ret) {
dev_err(dev, "failed to enable vpcie regulator\n");
return ret;
@@ -186,31 +437,49 @@ static int pcie_dw_imx_probe(struct udevice *dev)
return ret;
}
+ if (info->init_phy)
+ info->init_phy(priv);
+
+ imx_pcie_configure_type(priv);
+
ret = imx_pcie_clk_enable(priv);
if (ret) {
dev_err(dev, "failed to enable clocks\n");
goto err_clk;
}
- ret = generic_phy_init(&priv->phy);
- if (ret) {
- dev_err(dev, "failed to initialize PHY\n");
- goto err_phy_init;
- }
+ if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) {
+ ret = generic_phy_init(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to initialize PHY\n");
+ goto err_phy_init;
+ }
- ret = generic_phy_power_on(&priv->phy);
- if (ret) {
- dev_err(dev, "failed to power on PHY\n");
- goto err_phy_power;
+ ret = generic_phy_power_on(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power on PHY\n");
+ goto err_phy_power;
+ }
}
imx_pcie_deassert_core_reset(priv);
+ if (info->wait_pll_lock) {
+ ret = info->wait_pll_lock(priv);
+ if (ret) {
+ dev_err(dev, "failed to wait pll lock\n");
+ goto err_link;
+ }
+ }
+
+ if (info->post_config)
+ info->post_config(priv);
+
priv->dw.first_busno = dev_seq(dev);
priv->dw.dev = dev;
pcie_dw_setup_host(&priv->dw);
- if (pcie_link_up(priv, LINK_SPEED_GEN_1)) {
+ if (pcie_link_up(priv, priv->max_link_speed)) {
printf("PCIE-%d: Link down\n", dev_seq(dev));
ret = -ENODEV;
goto err_link;
@@ -229,26 +498,41 @@ static int pcie_dw_imx_probe(struct udevice *dev)
return 0;
err_link:
- generic_shutdown_phy(&priv->phy);
+ if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV)
+ generic_shutdown_phy(&priv->phy);
err_phy_power:
- generic_phy_exit(&priv->phy);
+ if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV)
+ generic_phy_exit(&priv->phy);
err_phy_init:
- clk_disable_bulk(&priv->clks);
+ clk_release_bulk(&priv->clks);
err_clk:
imx_pcie_deassert_core_reset(priv);
+ dm_gpio_free(dev, &priv->reset_gpio);
+
+ if (priv->vpcie)
+ regulator_set_enable_if_allowed(priv->vpcie, false);
+
return ret;
}
static int pcie_dw_imx_remove(struct udevice *dev)
{
struct pcie_dw_imx *priv = dev_get_priv(dev);
+ struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
+
+ if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV)
+ generic_shutdown_phy(&priv->phy);
- generic_shutdown_phy(&priv->phy);
dm_gpio_free(dev, &priv->reset_gpio);
- reset_free(&priv->apps_reset);
+ if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+ reset_free(&priv->apps_reset);
+
clk_release_bulk(&priv->clks);
+ if (priv->vpcie)
+ regulator_set_enable_if_allowed(priv->vpcie, false);
+
return 0;
}
@@ -257,7 +541,9 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
struct pcie_dw_imx *priv = dev_get_priv(dev);
ofnode gpr;
- int ret;
+ int ret, index;
+
+ priv->info = info;
/* Get the controller base address */
priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
@@ -274,17 +560,29 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
return -EINVAL;
}
+ priv->dw.atu_base = (void *)dev_read_addr_name_ptr(dev, "atu");
+ if (!priv->dw.atu_base)
+ dev_dbg(dev, "failed to get atu address from dtb\n");
+
ret = clk_get_bulk(dev, &priv->clks);
if (ret) {
dev_err(dev, "failed to get PCIe clks\n");
return ret;
}
- ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
- if (ret) {
- dev_err(dev,
- "Failed to get PCIe apps reset control\n");
- goto err_reset;
+ index = ofnode_stringlist_search(dev_ofnode(dev), "clock-names",
"ext-ref");
+ if (index < 0)
+ priv->enable_ext_refclk = false;
+ else
+ priv->enable_ext_refclk = true;
+
+ if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET) {
+ ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
+ if (ret) {
+ dev_err(dev,
+ "Failed to get PCIe apps reset control\n");
+ goto err_reset;
+ }
}
ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
@@ -294,26 +592,58 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
goto err_gpio;
}
- ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy);
- if (ret) {
- dev_err(dev, "failed to get pcie phy\n");
- goto err_phy;
+ if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) {
+ ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to get pcie phy\n");
+ goto err_phy;
+ }
}
- gpr = ofnode_by_compatible(ofnode_null(), info->gpr);
- if (ofnode_equal(gpr, ofnode_null())) {
- dev_err(dev, "unable to find GPR node\n");
- ret = -ENODEV;
- goto err_phy;
+ if (info->flags & IMX_PCIE_FLAG_HAS_SERDES) {
+ void __iomem *app_base;
+ fdt_size_t app_size;
+ struct regmap_config config;
+
+ app_base = (void *)dev_read_addr_size_name(dev, "app",
&app_size);
+ if ((fdt_addr_t)app_base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get app_base address\n");
+ return -EINVAL;
+ }
+
+ config.r_start = (ulong)app_base;
+ config.r_size = (ulong)app_size;
+ config.reg_offset_shift = 0;
+ config.width = REGMAP_SIZE_32;
+
+ priv->iomuxc_gpr = devm_regmap_init(dev, NULL, NULL, &config);
+ if (IS_ERR(priv->iomuxc_gpr)) {
+ dev_err(dev, "unable to remap gpr\n");
+ ret = PTR_ERR(priv->iomuxc_gpr);
+ goto err_phy;
+ }
}
- priv->iomuxc_gpr = syscon_node_to_regmap(gpr);
- if (IS_ERR(priv->iomuxc_gpr)) {
- dev_err(dev, "unable to find iomuxc registers\n");
- ret = PTR_ERR(priv->iomuxc_gpr);
- goto err_phy;
+ if (info->gpr) {
+ gpr = ofnode_by_compatible(ofnode_null(), info->gpr);
+ if (ofnode_equal(gpr, ofnode_null())) {
+ dev_err(dev, "unable to find GPR node\n");
+ ret = -ENODEV;
+ goto err_phy;
+ }
+
+ priv->iomuxc_gpr = syscon_node_to_regmap(gpr);
+ if (IS_ERR(priv->iomuxc_gpr)) {
+ dev_err(dev, "unable to find iomuxc registers\n");
+ ret = PTR_ERR(priv->iomuxc_gpr);
+ goto err_phy;
+ }
}
+ priv->max_link_speed = dev_read_u32_default(dev, "fsl,max-link-speed",
LINK_SPEED_GEN_1);
+
+ priv->supports_clkreq = dev_read_bool(dev, "supports-clkreq");
+
/* vpcie-supply regulator is optional */
device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie);
@@ -322,7 +652,8 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
err_phy:
dm_gpio_free(dev, &priv->reset_gpio);
err_gpio:
- reset_free(&priv->apps_reset);
+ if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+ reset_free(&priv->apps_reset);
err_reset:
clk_release_bulk(&priv->clks);
@@ -337,6 +668,7 @@ static const struct dm_pci_ops pcie_dw_imx_ops = {
static const struct udevice_id pcie_dw_imx_ids[] = {
{ .compatible = "fsl,imx8mm-pcie", .data = (ulong)&imx8mm_chip_info, },
{ .compatible = "fsl,imx8mp-pcie", .data = (ulong)&imx8mp_chip_info, },
+ { .compatible = "fsl,imx95-pcie", .data = (ulong)&imx95_chip_info, },
{ }
};
--
2.7.4
