On 06:32 Mon 21 Apr , Chee, Tien Fong wrote: > > > > -----Original Message----- > > From: Meng, Tingting <tingting.m...@altera.com> > > Sent: Monday, April 21, 2025 1:11 PM > > To: u-boot@lists.denx.de > > Cc: Marek Vasut <ma...@denx.de>; Chee, Tien Fong > > <tien.fong.c...@altera.com>; Meng, Tingting <tingting.m...@altera.com>; > > Hea, Kok Kiang <kok.kiang....@altera.com>; Maniyam, Dinesh > > <dinesh.mani...@altera.com>; Ng, Boon Khai <boon.khai...@altera.com>; > > Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@altera.com>; Rosdi, Danish > > Ahmad <danish.ahmad.ro...@altera.com>; Zamri, Muhammad Hazim Izzat > > <muhammad.hazim.izzat.za...@altera.com>; Lim, Jit Loon > > <jit.loon....@altera.com> > > Subject: [PATCH v1 1/5] arm: socfpga: agilex5: Add MMU mapping region > > > > From: Tingting Meng <tingting.m...@altera.com> > > > > MMU mapping regions were added for the second and third DDR memory > > banks. > > > > Signed-off-by: Tingting Meng <tingting.m...@altera.com> > > --- > > arch/arm/mach-socfpga/mmu-arm64_s10.c | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > [...] > Reviewed-by: Tien Fong Chee <tien.fong.c...@altera.com> > You can simply reply to cover letter to give all patches a Reviewed-by (No need to do for each)
and use tools like - b4 trailers to collect -- Yixun Lan (dlan)
