> -----Original Message-----
> From: Meng, Tingting <tingting.m...@altera.com>
> Sent: Monday, April 21, 2025 1:11 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <ma...@denx.de>; Chee, Tien Fong
> <tien.fong.c...@altera.com>; Meng, Tingting <tingting.m...@altera.com>;
> Hea, Kok Kiang <kok.kiang....@altera.com>; Maniyam, Dinesh
> <dinesh.mani...@altera.com>; Ng, Boon Khai <boon.khai...@altera.com>;
> Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@altera.com>; Rosdi, Danish
> Ahmad <danish.ahmad.ro...@altera.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.za...@altera.com>; Lim, Jit Loon
> <jit.loon....@altera.com>
> Subject: [PATCH v1 1/5] arm: socfpga: agilex5: Add MMU mapping region
>
> From: Tingting Meng <tingting.m...@altera.com>
>
> MMU mapping regions were added for the second and third DDR memory
> banks.
>
> Signed-off-by: Tingting Meng <tingting.m...@altera.com>
> ---
> arch/arm/mach-socfpga/mmu-arm64_s10.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-
> socfpga/mmu-arm64_s10.c
> index b8e40d9a788..1dc44ab4797 100644
> --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
> +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
> @@ -57,6 +57,20 @@ static struct mm_region socfpga_agilex5_mem_map[]
> = {
> .size = 0x80000000UL,
> .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> PTE_BLOCK_INNER_SHARE,
> + }, {
> + /* MEM 30GB */
> + .virt = 0x880000000UL,
> + .phys = 0x880000000UL,
> + .size = 0x780000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE,
> + }, {
> + /* MEM 480GB */
> + .virt = 0x8800000000UL,
> + .phys = 0x8800000000UL,
> + .size = 0x7800000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE,
> }, {
> /* List terminator */
> },
> --
> 2.25.1
Reviewed-by: Tien Fong Chee <tien.fong.c...@altera.com>
Best regards,
Tien Fong
