[PATCH v1 1/5] arm: socfpga: agilex5: Add MMU mapping region

[tingting . meng]

From: Tingting Meng <tingting.m...@altera.com>

MMU mapping regions were added for the second and third DDR memory banks.

Signed-off-by: Tingting Meng <tingting.m...@altera.com>
---
 arch/arm/mach-socfpga/mmu-arm64_s10.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c 
b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index b8e40d9a788..1dc44ab4797 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -57,6 +57,20 @@ static struct mm_region socfpga_agilex5_mem_map[] = {
                .size   = 0x80000000UL,
                .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
                                PTE_BLOCK_INNER_SHARE,
+       }, {
+               /* MEM 30GB */
+               .virt   = 0x880000000UL,
+               .phys   = 0x880000000UL,
+               .size   = 0x780000000UL,
+               .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                               PTE_BLOCK_INNER_SHARE,
+       }, {
+               /* MEM 480GB */
+               .virt   = 0x8800000000UL,
+               .phys   = 0x8800000000UL,
+               .size   = 0x7800000000UL,
+               .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                               PTE_BLOCK_INNER_SHARE,
        }, {
                /* List terminator */
        },
-- 
2.25.1