On Sun, Mar 2, 2025 at 1:53 PM Adam Ford <aford...@gmail.com> wrote:
>
> The ECSPI clock has the ability to select between pll3_60m and
> osc on the imx6qp, where it's fixed on other variants. Fix this
> by adding using a helper function to determine SoC variant and
> register the clock accordingly.
s/ESPI/ECSPI in the Subject.
> + if (clk_on_imx6qp()) {
> + clk_dm(IMX6QDL_CLK_ECSPI_SEL,
> + imx_clk_mux("ecspi_sel", base + 0x38, 18, 1,
> ecspi_sels,
> + ARRAY_SIZE(ecspi_sels)));
> + }
No need for { }.
> +
> clk_dm(IMX6QDL_CLK_USDHC1_PODF,
> imx_clk_divider("usdhc1_podf", "usdhc1_sel",
> base + 0x24, 11, 3));
> @@ -91,9 +103,13 @@ static int imx6q_clk_probe(struct udevice *dev)
> imx_clk_divider("usdhc4_podf", "usdhc4_sel",
> base + 0x24, 22, 3));
>
> - clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
> - imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
> -
> + if (clk_on_imx6qp()) {
> + clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
> + imx_clk_divider("ecspi_root", "ecspi_sel", base +
> 0x38, 19, 6));
> + } else {
> + clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
> + imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38,
> 19, 6));
> + }
Same here.
