[PATCH 02/10] clk: imx6q: Register UART clocks

[Adam Ford]

In order to use the driver model and clock system to enable UART
clocks from the serial driver, it's necessary to register the UART
clocks.  With the helper function to check for imx6qp vs other
variants, the UART can register for both scenarios.

Signed-off-by: Adam Ford <aford...@gmail.com>
---
 drivers/clk/imx/clk-imx6q.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index de5e5d8132b..caf20e2bc03 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -40,6 +40,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", 
"pll2_pfd0_352m", };
 static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
 static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
                                               "pll2_pfd0_352m", "pll2_198m", };
+static const char *const uart_sels[] = { "pll3_80m", "osc", };
 static const char *const ecspi_sels[] = { "pll3_60m", "osc", };
 
 static int imx6q_clk_probe(struct udevice *dev)
@@ -85,6 +86,9 @@ static int imx6q_clk_probe(struct udevice *dev)
                           usdhc_sels, ARRAY_SIZE(usdhc_sels)));
 
        if (clk_on_imx6qp()) {
+               clk_dm(IMX6QDL_CLK_UART_SEL,
+                      imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels,
+                                  ARRAY_SIZE(uart_sels)));
                clk_dm(IMX6QDL_CLK_ECSPI_SEL,
                       imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels,
                                   ARRAY_SIZE(ecspi_sels)));
@@ -104,9 +108,13 @@ static int imx6q_clk_probe(struct udevice *dev)
                               base + 0x24, 22, 3));
 
        if (clk_on_imx6qp()) {
+               clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+                      imx_clk_divider("uart_serial_podf", "uart_sel", base + 
0x24, 0, 6));
                clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
                       imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 
19, 6));
        } else {
+               clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF,
+                      imx_clk_divider("uart_serial_podf", "pll3_80m", base + 
0x24, 0, 6));
                clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
                       imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 
19, 6));
        }
@@ -118,6 +126,10 @@ static int imx6q_clk_probe(struct udevice *dev)
               imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
        clk_dm(IMX6QDL_CLK_ECSPI4,
               imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
+       clk_dm(IMX6QDL_CLK_UART_IPG,
+              imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24));
+       clk_dm(IMX6QDL_CLK_UART_SERIAL,
+              imx_clk_gate2("uart_serial", "uart_serial_podf",  base + 0x7c, 
26));
        clk_dm(IMX6QDL_CLK_USDHC1,
               imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
        clk_dm(IMX6QDL_CLK_USDHC2,
-- 
2.45.2