-----Original Message-----
From: alif.zakuan.yusla...@intel.com <alif.zakuan.yusla...@intel.com>
Sent: Tuesday, February 18, 2025 4:35 PM
To: u-boot@lists.denx.de
Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt
<simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong <tien.fong.c...@altera.com>;
Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@altera.com>; Meng, Tingting
<tingting.m...@altera.com>; Ng, Boon Khai <boon.khai...@altera.com>; Hea, Kok
Kiang <kok.kiang....@altera.com>; Alif Zakuan Yuslaimi
<alif.zakuan.yusla...@intel.com>; Zamri, Muhammad Hazim Izzat
<muhammad.hazim.izzat.za...@altera.com>
Subject: [PATCH v2 05/26] drivers: clk: agilex5: Set PLL to asynchronous mode
From: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@intel.com>
PLL frequency would overshoot from the original target in synchronous mode
during low VCC voltage condition.
To resolve this issue, PLL is set to run on asynchronous mode instead of
enabling synchronous mode in the clock driver.
Signed-off-by: Muhammad Hazim Izzat Zamri
<muhammad.hazim.izzat.za...@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com>
---
drivers/clk/altera/clk-agilex5.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c
index a284b562486..fb1e72ffc5c 100644
--- a/drivers/clk/altera/clk-agilex5.c
+++ b/drivers/clk/altera/clk-agilex5.c
@@ -72,15 +72,6 @@ static const struct {
u32 val;
u32 mask;
} membus_pll[] = {
- {
- MEMBUS_CLKSLICE_REG,
- /*
- * BIT[7:7]
- * Enable source synchronous mode
- */
- BIT(7),
- BIT(7)
- },
{
MEMBUS_SYNTHCALFOSC_INIT_CENTERFREQ_REG,
/*
--
2.25.1
Reviewed-by: Tien Fong Chee <tien.fong.c...@altera.com>
Best regards,
Tien Fong
