-----Original Message-----
From: alif.zakuan.yusla...@intel.com <alif.zakuan.yusla...@intel.com>
Sent: Tuesday, February 18, 2025 4:35 PM
To: u-boot@lists.denx.de
Cc: Marek Vasut <ma...@denx.de>; Simon Goldschmidt
<simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong <tien.fong.c...@altera.com>;
Yuslaimi, Alif Zakuan <alif.zakuan.yusla...@altera.com>; Meng, Tingting
<tingting.m...@altera.com>; Ng, Boon Khai <boon.khai...@altera.com>; Hea, Kok
Kiang <kok.kiang....@altera.com>; Alif Zakuan Yuslaimi
<alif.zakuan.yusla...@intel.com>
Subject: [PATCH v2 02/26] arm: socfpga: misc: Exclude Agilex5 from clock
manager base address retrieval
From: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@intel.com>
Agilex5 retrieves its clock manager address via probing its own clock driver
model during SPL initialization.
Therefore, excluding Agilex5 from calling generic clock driver in misc driver.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com>
---
v1->v2
- probe from DT for Agilex5 clock manager base address
---
arch/arm/mach-socfpga/misc.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index
9d464307665..fbe3af845d8 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
*/
#include <config.h>
@@ -248,15 +248,16 @@ void socfpga_get_managers_addr(void)
if (ret)
hang();
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
- ret = socfpga_get_base_addr("intel,agilex-clkmgr",
- &socfpga_clkmgr_base);
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
- ret = socfpga_get_base_addr("intel,n5x-clkmgr",
- &socfpga_clkmgr_base);
-#else
- ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
-#endif
+ if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
+ ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+ &socfpga_clkmgr_base);
+ else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
+ else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+ ret = socfpga_get_base_addr("altr,clk-mgr",
+ &socfpga_clkmgr_base);
+
if (ret)
hang();
}
--
2.25.1
Reviewed-by: Tien Fong Chee <tien.fong.c...@intel.com>
Best regards,
Tien Fong
