From: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@intel.com>

Agilex5 retrieves its clock manager address via probing its own clock
driver model during SPL initialization.

Therefore, excluding Agilex5 from calling generic clock driver in misc
driver.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yusla...@altera.com>

---

v1->v2
- probe from DT for Agilex5 clock manager base address
---
 arch/arm/mach-socfpga/misc.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 9d464307665..fbe3af845d8 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2025 Altera Corporation <www.altera.com>
  */
 
 #include <config.h>
@@ -248,15 +248,16 @@ void socfpga_get_managers_addr(void)
        if (ret)
                hang();
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-       ret = socfpga_get_base_addr("intel,agilex-clkmgr",
-                                   &socfpga_clkmgr_base);
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
-       ret = socfpga_get_base_addr("intel,n5x-clkmgr",
-                                   &socfpga_clkmgr_base);
-#else
-       ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
-#endif
+       if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
+               ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+                                           &socfpga_clkmgr_base);
+       else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+               ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+                                           &socfpga_clkmgr_base);
+       else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+               ret = socfpga_get_base_addr("altr,clk-mgr",
+                                           &socfpga_clkmgr_base);
+
        if (ret)
                hang();
 }
-- 
2.25.1

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