> -----Original Message----- > From: Valentin Longchamp [mailto:valentin.longch...@keymile.com] > Sent: Wednesday, May 04, 2011 9:24 PM > To: u-boot@lists.denx.de > Cc: holger.bru...@keymile.com; Prafulla Wadaskar; Valentin Longchamp; > Wolfgang Denk; Detlev Zundel > Subject: [PATCH v3 6/8] arm/km: rename mgcoge2un to mgcoge3un > > The mgcoge2un target was only an intermediate step to mgcoge3un. > For this reason the mgcoge2un support was moved to mgcoge3un, > because it isn't needed to support both targets. > > We add the BootROM init file for the mgcoge3un memphis RAM. > > We also move the suen3 and suen8 boards into the correct category > in the MAINTAINERS file. > > Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com> > Signed-off-by: Holger Brunck <holger.bru...@keymile.com> > Acked-by: Heiko Schocher <h...@denx.de> > cc: Wolfgang Denk <w...@denx.de> > cc: Detlev Zundel <d...@denx.de> > cc: Prafulla Wadaskar <prafu...@marvell.com> > --- > Changes for v2: > - split up first large patch series to three independent smaller > patch series > Changes for v3: > - taken Prafulla's comments into account, merged with previous 03/08 > patch > so that 03/08 does not look like dead code > > MAINTAINERS | 6 +- > board/keymile/km_arm/kwbimage-memphis.cfg | 197 > ++++++++++++++++++++++++++ > boards.cfg | 2 +- > include/configs/{mgcoge2un.h => mgcoge3un.h} | 15 ++- > 4 files changed, 210 insertions(+), 10 deletions(-) > create mode 100644 board/keymile/km_arm/kwbimage-memphis.cfg > rename include/configs/{mgcoge2un.h => mgcoge3un.h} (81%) > > diff --git a/MAINTAINERS b/MAINTAINERS > index e2a4ba9..39b3e78 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -430,13 +430,10 @@ Heiko Schocher <h...@denx.de> > kmsupx5 MPC8321 > mgcoge MPC8247 > mgcoge2ne MPC8247 > - mgcoge2un ARM926EJS (Kirkwood SoC) > mucmc52 MPC5200 > muas3001 MPC8270 > municse MPC5200 > sc3 PPC405GP > - suen3 ARM926EJS (Kirkwood SoC) > - suen8 ARM926EJS (Kirkwood SoC) > suvd3 MPC8321 > tuda1 MPC8321 > tuxa1 MPC8321 > @@ -814,6 +811,9 @@ Jens Scharsig <e...@bus-elektronik.de> > Heiko Schocher <h...@denx.de> > > magnesium i.MX27 > + mgcoge3un ARM926EJS (Kirkwood SoC) > + suen3 ARM926EJS (Kirkwood SoC) > + suen8 ARM926EJS (Kirkwood SoC) > > Robert Schwebel <r.schwe...@pengutronix.de> > > diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg > b/board/keymile/km_arm/kwbimage-memphis.cfg > new file mode 100644 > index 0000000..2faaf2b > --- /dev/null > +++ b/board/keymile/km_arm/kwbimage-memphis.cfg > @@ -0,0 +1,197 @@ > +# > +# (C) Copyright 2010 > +# Heiko Schocher, DENX Software Engineering, h...@denx.de. > +# > +# (C) Copyright 2011 > +# Valentin Longchamp, Keymile AG, valentin.longch...@keymile.com > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, > +# MA 02110-1301 USA > +# > +# Refer docs/README.kwimage for more details about how-to configure > +# and create kirkwood boot image > +# > + > +# Boot Media configurations > +BOOT_FROM spi # Boot from SPI flash > + > +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register > +# bit 3-0: MPPSel0 2, NF_IO[2] > +# bit 7-4: MPPSel1 2, NF_IO[3] > +# bit 12-8: MPPSel2 2, NF_IO[4] > +# bit 15-12: MPPSel3 2, NF_IO[5] > +# bit 19-16: MPPSel4 1, NF_IO[6] > +# bit 23-20: MPPSel5 1, NF_IO[7] > +# bit 27-24: MPPSel6 1, SYSRST_O > +# bit 31-28: MPPSel7 0, GPO[7] > + > +DATA 0xFFD10004 0x03303300 > + > +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register > +# bit 3-0: MPPSel16 0, GPIO[16] > +# bit 7-4: MPPSel17 0, GPIO[17] > +# bit 12-8: MPPSel18 1, NF_IO[0] > +# bit 15-12: MPPSel19 1, NF_IO[1] > +# bit 19-16: MPPSel20 0, GPIO[20] > +# bit 23-20: MPPSel21 0, GPIO[21] > +# bit 27-24: MPPSel22 0, GPIO[22] > +# bit 31-28: MPPSel23 0, GPIO[23] > + > +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register > +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register > +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register > +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register > +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register > +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register > + > +#Dram initalization > +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register > +# bit13-0: 0x4E0 (DDR2 clks refresh rate) > +# bit23-14: zero > +# bit24: 1= enable exit self refresh mode on DDR access > +# bit25: 1 required > +# bit29-26: zero > +# bit31-30: 01 > + > +DATA 0xFFD01404 0x38543000 # DDR Controller Control Low > +# bit 3-0: 0 reserved > +# bit 4: 0=addr/cmd in smame cycle > +# bit 5: 0=clk is driven during self refresh, we don't care for APX > +# bit 6: 0=use recommended falling edge of clk for addr/cmd > +# bit14: 0=input buffer always powered up > +# bit18: 1=cpu lock transaction enabled > +# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled > bit31=0 > +# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, > unbuffered DIMM > +# bit30-28: 3 required > +# bit31: 0=no additional STARTBURST delay > + > +DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value > +1) > +# bit3-0: TRAS lsbs > +# bit7-4: TRCD > +# bit11- 8: TRP > +# bit15-12: TWR > +# bit19-16: TWTR > +# bit20: TRAS msb > +# bit23-21: 0x0 > +# bit27-24: TRRD > +# bit31-28: TRTP > + > +DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) > +# bit6-0: TRFC > +# bit8-7: TR2R > +# bit10-9: TR2W > +# bit12-11: TW2W > +# bit31-13: zero required > + > +DATA 0xFFD01410 0x00000001 # DDR Address Control > +# bit1-0: 01, Cs0width=x16 > +# bit3-2: 00, Cs0size=2Gb > +# bit5-4: 00, Cs2width=nonexistent > +# bit7-6: 00, Cs1size =nonexistent > +# bit9-8: 00, Cs2width=nonexistent > +# bit11-10: 00, Cs2size =nonexistent > +# bit13-12: 00, Cs3width=nonexistent > +# bit15-14: 00, Cs3size =nonexistent > +# bit16: 0, Cs0AddrSel > +# bit17: 0, Cs1AddrSel > +# bit18: 0, Cs2AddrSel > +# bit19: 0, Cs3AddrSel > +# bit31-20: 0 required > + > +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control > +# bit0: 0, OpenPage enabled > +# bit31-1: 0 required > + > +DATA 0xFFD01418 0x00000000 # DDR Operation > +# bit3-0: 0x0, DDR cmd > +# bit31-4: 0 required > + > +DATA 0xFFD0141C 0x00000652 # DDR Mode > +DATA 0xFFD01420 0x00000006 # DDR Extended Mode > +# bit0: 0, DDR DLL enabled > +# bit1: 1, DDR drive strenght reduced > +# bit2: 1, DDR ODT control lsd disabled > +# bit5-3: 000, required > +# bit6: 0, DDR ODT control msb disabled > +# bit9-7: 000, required > +# bit10: 0, differential DQS enabled > +# bit11: 0, required > +# bit12: 0, DDR output buffer enabled > +# bit31-13: 0 required > + > +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High > +# bit2-0: 111, required > +# bit3 : 1 , MBUS Burst Chop disabled > +# bit6-4: 111, required > +# bit7 : 0 > +# bit8 : 1 , add a sample stage > +# bit9 : 0 , no half clock cycle addition to dataout > +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals > +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh > +# bit15-12: 1111 required > +# bit31-16: 0 required > + > +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low > +# bit3-0 : 0000, required > +# bit7-4 : 0010, M_ODT assertion 2 cycles after read > +# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read > +# bit15-12: 0100, internal ODT assertion 4 cycles after read > +# bit19-16: 1000, internal ODT de-assertion 8 cycles after read > +# bit31-20: 0 , required > + > +DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High > +# bit3-0 : 0001, M_ODT assertion same cycle as write > +# bit7-4 : 0101, M_ODT de-assertion x cycles after write > +# bit11-8 : 0100, internal ODT assertion x cycles after write > +# bit15-12: 1000, internal ODT de-assertion x cycles after write > + > +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 > +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size > +# bit0: 1, Window enabled > +# bit1: 0, Write Protect disabled > +# bit3-2: 00, CS0 hit selected > +# bit23-4: ones, required > +# bit31-24: 0x0F, Size (i.e. 256MB) > + > +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled > +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled > +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled > + > +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) > +# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 > +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 > + > +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) > +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above > +# bit3-2: 00, ODT1 controlled by register > +# bit31-4: zero, required > + > +DATA 0xFFD0149C 0x0000F801 # CPU ODT Control > +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 > +# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM > bank0 > +# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr > +# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm > +# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm > +# bit14 :1, STARTBURST ODT enabled > +# bit15 :1, Use ODT Block > + > +DATA 0xFFD01480 0x00000001 # DDR Initialization Control > +# bit0=1, enable DDR init upon this register write > + > +# End of Header extension > +DATA 0x0 0x0 > diff --git a/boards.cfg b/boards.cfg > index 2b0900a..2d36c52 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -105,7 +105,7 @@ davinci_sffsdr arm arm926ejs > sffsdr davinci > davinci_sonata arm arm926ejs sonata > davinci davinci > suen3 arm arm926ejs km_arm > keymile kirkwood > suen8 arm arm926ejs km_arm > keymile kirkwood > -mgcoge2un arm arm926ejs km_arm > keymile kirkwood > +mgcoge3un arm arm926ejs km_arm > keymile kirkwood > guruplug arm arm926ejs - > Marvell kirkwood > mv88f6281gtw_ge arm arm926ejs - > Marvell kirkwood > openrd_base arm arm926ejs - > Marvell kirkwood > diff --git a/include/configs/mgcoge2un.h b/include/configs/mgcoge3un.h > similarity index 81% > rename from include/configs/mgcoge2un.h > rename to include/configs/mgcoge3un.h > index 876ac34..1c32085 100644 > --- a/include/configs/mgcoge2un.h > +++ b/include/configs/mgcoge3un.h > @@ -31,8 +31,8 @@ > /* for linking errors see > * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ > > -#ifndef _CONFIG_MGCOGE2UN_H > -#define _CONFIG_MGCOGE2UN_H > +#ifndef _CONFIG_MGCOGE3UN_H > +#define _CONFIG_MGCOGE3UN_H > > /* include common defines/options for all arm based Keymile boards */ > #include "km_arm.h" > @@ -40,11 +40,14 @@ > /* > * Version number information > */ > -#define CONFIG_IDENT_STRING "\nKeymile MGCOGE2UN" > - > -#define CONFIG_HOSTNAME mgcoge2un > +#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN" > +#define CONFIG_HOSTNAME mgcoge3un > +#define CONFIG_MGCOGE3UN > > #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ > #define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ > > -#endif /* _CONFIG_MGCOGE2UN_H */ > +/* we use a new RAM type on mgcoge3un board */ > +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage- > memphis.cfg > + > +#endif /* _CONFIG_MGCOGE3UN_H */
Acked-by: Prafulla Wadaskar <prafu...@marvell.com> Regards.. Prafulla . . _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
