[U-Boot] [PATCH 1/4] Serial: pl011: new vendor init options

[John Rigby]

Two new options:

CONFIG_PL011_SERIAL_RLCR

Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500)
have separate receive and transmit line control registers.  Set
this variable to initialize the extra register.

CONFIG_PL011_SERIAL_FLUSH_ON_INIT

On some platforms (e.g. U8500) U-Boot is loaded by a second stage
boot loader that has already initialized the UART.  Define this
variable to flush the UART at init time.
empty fifo on init

Signed-off-by: John Rigby <john.ri...@linaro.org>
Signed-off-by: Rabin Vincent <rabin.vinc...@stericsson.com>
---
v2: No changes
v3: Enable changes with new CONFIG_* options instead of platform.
Document new CONFIG_* options in README.
v4: Added delay before writing to RLCR.
Removed Rabin as author at his request.
v5: Fixed commit message p1011 to pl011

 README                        |   12 ++++++++++++
 drivers/serial/serial_pl01x.c |   30 +++++++++++++++++++++++++++---
 drivers/serial/serial_pl01x.h |    4 ++++
 3 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/README b/README
index 76b1500..68ef2b2 100644
--- a/README
+++ b/README
@@ -475,6 +475,18 @@ The following options need to be configured:
                define this to a list of base addresses for each (supported)
                port. See e.g. include/configs/versatile.h
 
+               CONFIG_PL011_SERIAL_RLCR
+
+               Some vendor versions of PL011 serial ports (e.g. ST-Ericsson 
U8500)
+               have separate receive and transmit line control registers.  Set
+               this variable to initialize the extra register.
+
+               CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+
+               On some platforms (e.g. U8500) U-Boot is loaded by a second 
stage
+               boot loader that has already initialized the UART.  Define this
+               variable to flush the UART at init time.
+
 
 - Console Interface:
                Depending on board, define exactly one serial port
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 5dfcde8..7a064ff 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -111,6 +111,15 @@ int serial_init (void)
        unsigned int divider;
        unsigned int remainder;
        unsigned int fraction;
+       unsigned int lcr;
+
+#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+       /* Empty RX fifo if necessary */
+       if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
+               while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
+                       readl(&regs->dr);
+       }
+#endif
 
        /* First, disable everything */
        writel(0, &regs->pl011_cr);
@@ -131,9 +140,24 @@ int serial_init (void)
        writel(fraction, &regs->pl011_fbrd);
 
        /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
-       writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN,
-              &regs->pl011_lcrh);
-
+       lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+       writel(lcr, &regs->pl011_lcrh);
+
+#ifdef CONFIG_PL011_SERIAL_RLCR
+       {
+               int i;
+
+               /*
+                * Program receive line control register after waiting
+                * 10 bus cycles.  Delay be writing to readonly register
+                * 10 times
+                */
+               for (i = 0; i < 10; i++)
+                       writel(lcr, &regs->fr);
+
+               writel(lcr, &regs->pl011_rlcr);
+       }
+#endif
        /* Finally, enable the UART */
        writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
               &regs->pl011_cr);
diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h
index b670c24..96ee381 100644
--- a/drivers/serial/serial_pl01x.h
+++ b/drivers/serial/serial_pl01x.h
@@ -43,7 +43,11 @@ struct pl01x_regs {
        u32     pl010_lcrl;     /* 0x10 Line control register, low byte */
        u32     pl010_cr;       /* 0x14 Control register */
        u32     fr;             /* 0x18 Flag register (Read only) */
+#ifdef CONFIG_PL011_SERIAL_RLCR
+       u32     pl011_rlcr;     /* 0x1c Receive line control register */
+#else
        u32     reserved;
+#endif
        u32     ilpr;           /* 0x20 IrDA low-power counter register */
        u32     pl011_ibrd;     /* 0x24 Integer baud rate register */
        u32     pl011_fbrd;     /* 0x28 Fractional baud rate register */
-- 
1.7.1

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