Update node-names according to DTspec. Add labels for compatibility
and/or add missing nodes in order to make the file compatible with the
corresponding counterpart in dts/upstream. Eventually the u-boot local
file then can be replaced by the dts/upstream, and eventually removed.
Signed-off-by: Lothar Rubusch <l.rubu...@gmail.com>
---
arch/arm/dts/socfpga_arria10.dtsi | 42 ++++++++++++++++++++++++-------
1 file changed, 33 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/arm/dts/socfpga_arria10.dtsi
index bab34ab56c..5826268823 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -15,13 +15,13 @@
#size-cells = <0>;
enable-method = "altr,socfpga-a10-smp";
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
@@ -29,7 +29,16 @@
};
};
- intc: intc@ffffd000 {
+ pmu: pmu@ff111000 {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&intc>;
+ interrupts = <0 124 4>, <0 125 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ reg = <0xff111000 0x1000>,
+ <0xff113000 0x1000>;
+ };
+
+ intc: interrupt-controller@ffffd000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
@@ -73,7 +82,7 @@
};
};
- base_fpga_region {
+ fpga-region {
#address-cells = <0x1>;
#size-cells = <0x1>;
@@ -638,7 +647,7 @@
reg = <0xffcfb100 0x80>;
};
- L2: l2-cache@fffff000 {
+ L2: cache-controller@fffff000 {
compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>;
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -649,7 +658,7 @@
arm,shared-override;
};
- mmc: dwmmc0@ff808000 {
+ mmc: mmc@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
@@ -662,7 +671,7 @@
status = "disabled";
};
- nand: nand@ffb90000 {
+ nand: nand-controller@ffb90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-denali-nand";
@@ -729,6 +738,16 @@
<37 IRQ_TYPE_LEVEL_HIGH>;
};
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
@@ -760,6 +779,11 @@
resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
reset-names = "qspi", "qspi-ocp";
status = "disabled";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ };
};
rst: rstmgr@ffd05000 {
@@ -828,7 +852,7 @@
reset-names = "timer";
};
- uart0: serial0@ffc02000 {
+ uart0: serial@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -839,7 +863,7 @@
status = "disabled";
};
- uart1: serial1@ffc02100 {
+ uart1: serial@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
--
2.25.1
