The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at
multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V.
rzg2l_pinconf_set() is extended to support the 2.5V setting, with a
check to ensure this is only used on Ethernet interfaces as it is not
supported on the SD & QSPI interfaces.
While we're modifying rzg2l_pinconf_set(), drop the unnecessary default
value for pwr_reg as it is set in every branch of the following if
condition.
Signed-off-by: Paul Barker <paul.barker...@bp.renesas.com>
---
drivers/pinctrl/renesas/rzg2l-pfc.c | 49 ++++++++++++++++++++---------
include/renesas/rzg2l-pfc.h | 2 ++
2 files changed, 37 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c
b/drivers/pinctrl/renesas/rzg2l-pfc.c
index e88ec1c18373..0098e2d52d57 100644
--- a/drivers/pinctrl/renesas/rzg2l-pfc.c
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -394,18 +394,10 @@ static int rzg2l_pinconf_set(struct udevice *dev,
unsigned int pin_selector,
}
case PIN_CONFIG_POWER_SOURCE: {
- u32 pwr_reg = 0x0;
+ bool support_2500 = false;
+ u32 pwr_reg;
+ u32 value;
- /* argument is in mV */
- if (argument != 1800 && argument != 3300) {
- dev_err(dev, "Invalid mV %u\n", argument);
- return -EINVAL;
- }
-
- /*
- * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be
- * handled when the RZ/G2L Ethernet driver is added.
- */
if (cfg & PIN_CFG_IO_VMC_SD0) {
dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n",
port_offset, pin, argument);
@@ -418,13 +410,42 @@ static int rzg2l_pinconf_set(struct udevice *dev,
unsigned int pin_selector,
dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n",
port_offset, pin, argument);
pwr_reg = QSPI;
+ } else if (cfg & PIN_CFG_IO_VMC_ETH0) {
+ dev_dbg(dev, "port off %u:%u set ETH0 PVDD=%u\n",
+ port_offset, pin, argument);
+ pwr_reg = ETH_POC(0);
+ support_2500 = true;
+ } else if (cfg & PIN_CFG_IO_VMC_ETH1) {
+ dev_dbg(dev, "port off %u:%u set ETH1 PVDD=%u\n",
+ port_offset, pin, argument);
+ pwr_reg = ETH_POC(1);
+ support_2500 = true;
} else {
- dev_dbg(dev, "pin power source is not selectable\n");
+ dev_dbg(dev, "port off %u:%u PVDD is not selectable\n",
+ port_offset, pin);
+ return -EINVAL;
+ }
+
+ /* argument is in mV */
+ switch (argument) {
+ case 1800:
+ value = PVDD_1800;
+ break;
+ case 3300:
+ value = PVDD_3300;
+ break;
+ case 2500:
+ if (support_2500) {
+ value = PVDD_2500;
+ break;
+ }
+ fallthrough;
+ default:
+ dev_err(dev, "Invalid mV %u\n", argument);
return -EINVAL;
}
- writel((argument == 1800) ? PVDD_1800 : PVDD_3300,
- data->base + pwr_reg);
+ writel(value, data->base + pwr_reg);
break;
}
diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h
index 2df17ece2a31..d1015b1d2ac1 100644
--- a/include/renesas/rzg2l-pfc.h
+++ b/include/renesas/rzg2l-pfc.h
@@ -77,9 +77,11 @@
#define IEN(n) (0x1800 + (n) * 8)
#define PWPR 0x3014
#define SD_CH(n) (0x3000 + (n) * 4)
+#define ETH_POC(ch) (0x300c + (ch) * 4)
#define QSPI 0x3008
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
+#define PVDD_2500 2 /* I/O domain voltage 2.5V */
#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
#define PWPR_B0WI BIT(7) /* Bit Write Disable */
--
2.43.0
