On Tue, Apr 12, 2011 at 3:29 AM, Stefano Babic <sba...@denx.de> wrote:
> On 04/11/2011 03:05 PM, Ben Gardiner wrote:
>>
>>> [...]
>>> @@ -143,20 +144,20 @@ int board_init(void)
>>> irq_init();
>>> #endif
>>>
>>> -#ifdef CONFIG_NAND_DAVINCI
>>> /*
>>> * NAND CS setup - cycle counts based on da850evm NAND timings in the
>>> * Linux kernel @ 25MHz EMIFA
>>> */
>>> +#ifdef CONFIG_NAND_DAVINCI
>>> writel((DAVINCI_ABCR_WSETUP(0) |
>>> - DAVINCI_ABCR_WSTROBE(0) |
>>> + DAVINCI_ABCR_WSTROBE(1) |
>>
>> If WSTROBE is modified then the timings are no longer solely based on
>> the NAND timings in arch/arm/mach-davinci/board-da850-evm.c in the
>> Linux kernel. Can you add an amendment to the comment describing the
>> motivation for the extra WSTROBE cycle?
>
> Really this board will not use at all the board-da850-evm.c, but (no
> patches are yet pushed) it will have its own board configuration file
> (something like arch/arm/mach-davinci/ea20.c). I understand that if no
Ok. I understand that the ea20 is not the da850evm. I think that if
the comment says "based on da850evm NAND timings" then any change from
those timings should also be noted.
> [...]
> Regarding setting the WSTROBE, I understood from manual
> (EMIFA) that WSTROBE and RSTROBE cannot be set to zero if the EMA_WAIT
> pin is used, as on this board.
Yes, you're absolutely right:
"
Finally, a restriction is placed on the strobe period timing
parameters when operating in Extended Wait
mode. Specifically, the W_STROBE and R_STROBE fields must not be set
to 0 for proper operation.
" [1]
Thanks, Stefano! -- I got it wrong in commit
a3f88293ddd13facd734769c1664d35ab4ed681f da850evm: setup the NAND
flash timings
I just re-inspected the settings assigned by
davinci_aemif_setup_timing() in arch/arm/mach-davinci/aemif.c of the
Linux kernel and they are:
wsetup=0
wstrobe=1
whold=0
rsetup=0
rstrobe=1
rhold=0
ta=1
So 'WSTROBE'(0) and 'TA(0)' need to be fixed in
board/davinci/da8xxevm/da850evm.c. Patch coming.
I think this means you should also update to TA(1) in your patch --
although it really depends on what the ea20 NAND chip timings are.
Best Regards,
Ben Gardiner
[1] http://www.ti.com/litv/pdf/sprufl6f
---
Nanometrics Inc.
http://www.nanometrics.ca
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