Hi Mingkai,
2011/1/27 Mingkai Hu <mingkai...@freescale.com>
> Port from tsec.c file to add support for m88e1011s, m88e1111s, m88e1118,
> m88e1121r, m88e1145, m88e1149s.
>
> Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
> ---
> drivers/net/fsl_phy.c | 299
> +++++++++++++++++++++++++++++++++++++++++++++++++
> drivers/net/fsl_phy.h | 36 ++++++
> 2 files changed, 335 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
> index 7c22666..ad9d65e 100644
> --- a/drivers/net/fsl_phy.c
> +++ b/drivers/net/fsl_phy.c
> @@ -457,6 +457,245 @@ static int bcm5482_startup(struct mii_info *mii_info)
> return 0;
> }
>
> +/* Marvell 88E1011S */
> +static int m88e1011s_config(struct mii_info *mii_info)
> +{
> + /* Reset and configure the PHY */
> + tsec_phy_write(mii_info, 0, MII_BMCR, BMCR_RESET);
> +
> + tsec_phy_write(mii_info, 0, 0x1d, 0x1f);
> + tsec_phy_write(mii_info, 0, 0x1e, 0x200c);
> + tsec_phy_write(mii_info, 0, 0x1d, 0x5);
> + tsec_phy_write(mii_info, 0, 0x1e, 0);
> + tsec_phy_write(mii_info, 0, 0x1e, 0x100);
> + tsec_phy_write(mii_info, 0, MII_CTRL1000, MII_CTRL1000_INIT);
> + tsec_phy_write(mii_info, 0, MII_ADVERTISE, MII_ADVERTISE_INIT);
> +
> + tsec_phy_write(mii_info, 0, MII_BMCR, BMCR_RESET);
> + tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
> +
> + return 0;
> +}
>
Is this possible to assign the clear definition about bit fields with phy
registers
rather than hard-code hex value?
I think clear definitions will help both other vendor and your customers,
whom are the ODM/OEM vendors is easier to debug with these phy chips.
Hope you can agree with this suggestions.
--
Best regards,
Macpaul Lin
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