Port from tsec.c file to add support for bcm5461, bcm5464, bcm5482s.
Signed-off-by: Mingkai Hu <mingkai...@freescale.com>
---
drivers/net/fsl_phy.c | 245 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/net/fsl_phy.h | 22 +++++
2 files changed, 267 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
index a6ec614..7c22666 100644
--- a/drivers/net/fsl_phy.c
+++ b/drivers/net/fsl_phy.c
@@ -21,6 +21,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
+#include <tsec.h>
#include "fsl_phy.h"
@@ -242,6 +243,220 @@ static int genphy_shutdown(struct mii_info *phydev)
return 0;
}
+/* Broadcom BCM5461S */
+static int bcm5461_config(struct mii_info *mii_info)
+{
+ unsigned int reg;
+
+ /* reset the PHY */
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_RESET;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ tsec_phy_write(mii_info, 0, MII_CTRL1000, MII_CTRL1000_INIT);
+ tsec_phy_write(mii_info, 0, MII_ADVERTISE, MII_ADVERTISE_INIT);
+
+ /* reset the PHY */
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_RESET;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ return 0;
+}
+
+static int bcm54xx_parse_status(struct mii_info *mii_info)
+{
+ unsigned int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_BCM54xx_AUXSTATUS);
+
+ switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
+ MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
+ case 1:
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_10;
+ break;
+ case 2:
+ mii_info->duplex = DUPLEX_FULL;
+ mii_info->speed = SPEED_10;
+ break;
+ case 3:
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_100;
+ break;
+ case 5:
+ mii_info->duplex = DUPLEX_FULL;
+ mii_info->speed = SPEED_100;
+ break;
+ case 6:
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_1000;
+ break;
+ case 7:
+ mii_info->duplex = DUPLEX_FULL;
+ mii_info->speed = SPEED_1000;
+ break;
+ default:
+ printf("Auto-neg error, defaulting to 10BT/HD\n");
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_10;
+ break;
+ }
+
+ return 0;
+}
+
+static int bcm54xx_startup(struct mii_info *mii_info)
+{
+ /* Read the Status (2x to make sure link is right) */
+ genphy_update_link(mii_info);
+ bcm54xx_parse_status(mii_info);
+
+ return 0;
+}
+
+/* Broadcom BCM5482S */
+/*
+ * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
+ * circumstances. eg a gigabit TSEC connected to a gigabit switch with
+ * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
+ * link. "Ethernet@Wirespeed" reduces advertised speed until link
+ * can be achieved.
+ */
+static u32 bcm5482_read_wirespeed(struct mii_info *mii_info, u32 reg)
+{
+ return (tsec_phy_read(mii_info, 0, reg) & 0x8FFF) | 0x8010;
+}
+
+static int bcm5482_config(struct mii_info *mii_info)
+{
+ unsigned int reg;
+
+ /* reset the PHY */
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_RESET;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ /* Setup read from auxilary control shadow register 7 */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54xx_AUXCNTL,
+ MIIM_BCM54xx_AUXCNTL_ENCODE(7));
+ /* Read Misc Control register and or in Ethernet@Wirespeed */
+ reg = bcm5482_read_wirespeed(mii_info, MIIM_BCM54xx_AUXCNTL);
+ tsec_phy_write(mii_info, 0, MIIM_BCM54xx_AUXCNTL, reg);
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+ /* Initial config/enable of secondary SerDes interface */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_SHD,
+ MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf));
+ /* Write intial value to secondary SerDes Contol */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_EXP_SEL,
+ MIIM_BCM54XX_EXP_SEL_SSD | 0);
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_EXP_DATA, MII_BMCR_RESTART);
+ /* Enable copper/fiber auto-detect */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_SHD,
+ MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201));
+
+ return 0;
+}
+
+/*
+ * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
+ * 0x42 - "Operating Mode Status Register"
+ */
+static int bcm5482_is_serdes(struct mii_info *mii_info)
+{
+ u16 val;
+ int serdes = 0;
+
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_EXP_SEL,
+ MIIM_BCM54XX_EXP_SEL_ER | 0x42);
+ val = tsec_phy_read(mii_info, 0, MIIM_BCM54XX_EXP_DATA);
+
+ switch (val & 0x1f) {
+ case 0x0d: /* RGMII-to-100Base-FX */
+ case 0x0e: /* RGMII-to-SGMII */
+ case 0x0f: /* RGMII-to-SerDes */
+ case 0x12: /* SGMII-to-SerDes */
+ case 0x13: /* SGMII-to-100Base-FX */
+ case 0x16: /* SerDes-to-Serdes */
+ serdes = 1;
+ break;
+ case 0x6: /* RGMII-to-Copper */
+ case 0x14: /* SGMII-to-Copper */
+ case 0x17: /* SerDes-to-Copper */
+ break;
+ default:
+ printf("ERROR, invalid PHY mode (0x%x\n)", val);
+ break;
+ }
+
+ return serdes;
+}
+
+/*
+ * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
+ * Mode Status Register"
+ */
+static u32 bcm5482_parse_serdes_sr(struct mii_info *mii_info)
+{
+ u16 val;
+ int i = 0;
+
+ /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
+ while (1) {
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_EXP_SEL,
+ MIIM_BCM54XX_EXP_SEL_ER | 0x42);
+ val = tsec_phy_read(mii_info, 0, MIIM_BCM54XX_EXP_DATA);
+
+ if (val & 0x8000)
+ break;
+
+ if (i++ > 1000) {
+ mii_info->link = 0;
+ return 1;
+ }
+
+ udelay(1000); /* 1 ms */
+ }
+
+ mii_info->link = 1;
+ switch ((val >> 13) & 0x3) {
+ case (0x00):
+ mii_info->speed = 10;
+ break;
+ case (0x01):
+ mii_info->speed = 100;
+ break;
+ case (0x02):
+ mii_info->speed = 1000;
+ break;
+ }
+
+ mii_info->duplex = (val & 0x1000) == 0x1000;
+
+ return 0;
+}
+
+/*
+ * Figure out if BCM5482 is in serdes or copper mode and determine link
+ * configuration accordingly
+ */
+static int bcm5482_startup(struct mii_info *mii_info)
+{
+ if (bcm5482_is_serdes(mii_info)) {
+ bcm5482_parse_serdes_sr(mii_info);
+ mii_info->flags |= TSEC_FIBER;
+ } else {
+ /* Wait for auto-negotiation to complete or fail */
+ genphy_update_link(mii_info);
+ /* Parse BCM54xx copper aux status register */
+ bcm54xx_parse_status(mii_info);
+ }
+
+ return 0;
+}
+
/* Vitesse VSC8211 */
static int vsc8211_config(struct mii_info *mii_info)
{
@@ -359,6 +574,33 @@ int vsc8601_config(struct mii_info *mii_info)
return 0;
}
+static struct phy_info phy_info_BCM5461S = {
+ "Broadcom BCM5461S",
+ 0x2060c0,
+ 0xfffff0,
+ &bcm5461_config,
+ &bcm54xx_startup,
+ &genphy_shutdown,
+};
+
+static struct phy_info phy_info_BCM5464S = {
+ "Broadcom BCM5464S",
+ 0x2060b0,
+ 0xfffff0,
+ &bcm5461_config,
+ &bcm54xx_startup,
+ &genphy_shutdown,
+};
+
+static struct phy_info phy_info_BCM5482S = {
+ "Broadcom BCM5482S",
+ 0x143bcb0,
+ 0xffffff0,
+ &bcm5482_config,
+ &bcm5482_startup,
+ &genphy_shutdown,
+};
+
static struct phy_info phy_info_VSC8211 = {
"Vitesse VSC8211",
0xfc4b0,
@@ -423,6 +665,9 @@ static struct phy_info phy_info_generic = {
};
static struct phy_info *phy_info[] = {
+ &phy_info_BCM5461S,
+ &phy_info_BCM5464S,
+ &phy_info_BCM5482S,
&phy_info_VSC8211,
&phy_info_VSC8221,
&phy_info_VSC8244,
diff --git a/drivers/net/fsl_phy.h b/drivers/net/fsl_phy.h
index d18cc58..340527c 100644
--- a/drivers/net/fsl_phy.h
+++ b/drivers/net/fsl_phy.h
@@ -38,7 +38,9 @@
#define PHY_EXT_PAGE_ACCESS 0x1f
#define MII_BMCR_INIT 0x00001140
+#define MII_BMCR_RESTART 0x00001340
#define MII_ADVERTISE_INIT 0x1e1
+#define MII_CTRL1000_INIT 0xe00
/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT 0x80000000
@@ -100,6 +102,26 @@
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
+/* Broadcom BCM54xx -- taken from linux sungem_phy */
+#define MIIM_BCM54xx_AUXCNTL 0x18
+#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7)
+#define MIIM_BCM54xx_AUXSTATUS 0x19
+#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
+#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
+
+#define MIIM_BCM54XX_SHD 0x1c
+#define MIIM_BCM54XX_SHD_WRITE 0x8000
+#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
+#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
+#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
+ (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
+ MIIM_BCM54XX_SHD_DATA(data))
+
+#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
+#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
+#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
+#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register
select */
+
/* Cicada Auxiliary Control/Status Register */
#define MIIM_CIS8201_AUX_CONSTAT 0x1c
#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
--
1.6.4
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