On Mon, Dec 20, 2010 at 9:08 AM, John Rigby <john.ri...@linaro.org> wrote: > Earlier in this thread Alexander said: >> I haven't add the definitions which are using a memory barrier because I >> haven't found >> a place in the kernel where they were actually enabled >> (CONFIG_ARM_DMA_MEM_BUFFERABLE). > > I think this is the problem because it is indeed defined for all v6 > and v7 arm platforms. Here is the config snippet from > arch/arm/mm/Kconfig: > > config ARM_DMA_MEM_BUFFERABLE > bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7 > depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ > MACH_REALVIEW_PB11MP) > default y if CPU_V6 || CPU_V7 > help > Historically, the kernel has used strongly ordered mappings to > provide DMA coherent memory. With the advent of ARMv7, mapping > memory with differing types results in unpredictable behaviour, > so on these CPUs, this option is forced on.
On second thought maybe this is noise for us in u-boot without cacheable mappings? Sorry for the noise. br, John _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
