> -----Original Message----- > From: Maniyam, Dinesh <[email protected]> > Sent: Tuesday, 31 May, 2022 4:06 PM > To: [email protected] > Cc: Chee, Tien Fong <[email protected]>; Hea, Kok Kiang > <[email protected]>; Gan, Yau Wai <[email protected]>; Kho, > Sin Hui <[email protected]>; Lokanathan, Raaj > <[email protected]>; Maniyam, Dinesh > <[email protected]> > Subject: [PATCH] arm: dts: socfpga: agilex: Add freeze controller node > > From: Dinesh Maniyam <[email protected]> > > The freeze controller is required for FPGA partial reconfig. > This node is disable on default. > Enable this node via u-boot fdt command when needed. > > Signed-off-by: Yau Wai Gan <[email protected]> > Signed-off-by: Dinesh Maniyam <[email protected]> > --- > arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi > b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi > index 6cac36a1fc..2400fad18a 100644 > --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi > +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi > @@ -2,7 +2,7 @@ > /* > * U-Boot additions > * > - * Copyright (C) 2019 Intel Corporation <www.intel.com> > + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> > */ > > #include "socfpga_agilex-u-boot.dtsi" > @@ -11,6 +11,15 @@ > aliases { > spi0 = &qspi; > i2c0 = &i2c1; > + freeze_br0 = &freeze_controller; > + }; > + > + soc { > + freeze_controller: freeze_controller@f9000450 { > + compatible = "altr,freeze-bridge-controller"; > + reg = <0xf9000450 0x00000010>; > + status = "disabled"; > + }; > }; > > memory { > -- > 2.26.2
Reviewed-by: Tien Fong Chee <[email protected]> Regards Tien Fong
