Hi Marek, Thank you for the patch.
On Wed, Apr 28, 2021 at 8:30 PM Marek Vasut <[email protected]> wrote: > > From: Hai Pham <[email protected]> > > This supports RPCD2 clock handling. While at it, add the check point > for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd > number > > Signed-off-by: Hai Pham <[email protected]> > Signed-off-by: Marek Vasut <[email protected]> > --- > drivers/clk/renesas/clk-rcar-gen3.c | 19 ++++++++++++++----- > drivers/clk/renesas/rcar-gen3-cpg.h | 3 +++ > 2 files changed, 17 insertions(+), 5 deletions(-) > Tested on RZ/G2E board Tested-by: Lad Prabhakar <[email protected]> Cheers, Prabhakar > diff --git a/drivers/clk/renesas/clk-rcar-gen3.c > b/drivers/clk/renesas/clk-rcar-gen3.c > index 09d84c44e1..763e268937 100644 > --- a/drivers/clk/renesas/clk-rcar-gen3.c > +++ b/drivers/clk/renesas/clk-rcar-gen3.c > @@ -289,6 +289,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk) > return -EINVAL; > > case CLK_TYPE_GEN3_RPC: > + case CLK_TYPE_GEN3_RPCD2: > rate = gen3_clk_get_rate64(&parent); > > value = readl(priv->base + core->offset); > @@ -304,13 +305,21 @@ static u64 gen3_clk_get_rate64(struct clk *clk) > > postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & > CPG_RPC_POSTDIV_MASK; > - rate /= postdiv + 1; > > - debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => > rate=%llu\n", > - __func__, __LINE__, > - core->parent, prediv, postdiv, rate); > + if (postdiv % 2 != 0) { > + rate /= postdiv + 1; > > - return rate; > + if (core->type == CLK_TYPE_GEN3_RPCD2) > + rate /= 2; > + > + debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i > => rate=%llu\n", > + __func__, __LINE__, > + core->parent, prediv, postdiv, rate); > + > + return rate; > + } > + > + return -EINVAL; > > } > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h > b/drivers/clk/renesas/rcar-gen3-cpg.h > index 8265c96cf6..52526a0cab 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.h > +++ b/drivers/clk/renesas/rcar-gen3-cpg.h > @@ -35,6 +35,9 @@ enum rcar_gen3_clk_types { > #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ > DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) > > +#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \ > + DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset) > + > #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ > DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ > (_parent0) << 16 | (_parent1), \ > -- > 2.30.2 >
