On Mon, Dec 28, 2020 at 7:28 AM Peng Fan (OSS) <peng....@oss.nxp.com> wrote:
>
> From: Peng Fan <peng....@nxp.com>
>
> Move SP to end of OCRAM space. Drop MALLOC_F to make it alloc from
> stack space.
>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> ---
> drivers/power/power_i2c.c | 8 ++++----
> include/configs/imx8mn_evk.h | 9 +++------
> 2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c
> index 5a0455e119..b67ac2f027 100644
> --- a/drivers/power/power_i2c.c
> +++ b/drivers/power/power_i2c.c
> @@ -23,7 +23,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
>
> if (check_reg(p, reg))
> return -EINVAL;
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> struct udevice *dev;
> int ret;
>
> @@ -67,7 +67,7 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
> return -EINVAL;
> }
>
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> return dm_i2c_write(dev, reg, buf, pmic_i2c_tx_num);
> #else
> return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num);
> @@ -83,7 +83,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
> if (check_reg(p, reg))
> return -EINVAL;
>
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> struct udevice *dev;
>
> ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr,
> @@ -131,7 +131,7 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
> int pmic_probe(struct pmic *p)
> {
> debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name);
> -#if defined(CONFIG_DM_I2C)
> +#if CONFIG_IS_ENABLED(DM_I2C)
> struct udevice *dev;
> int ret;
>
> diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
> index a6333085fe..61db244e98 100644
> --- a/include/configs/imx8mn_evk.h
> +++ b/include/configs/imx8mn_evk.h
> @@ -20,17 +20,14 @@
> (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
>
> #ifdef CONFIG_SPL_BUILD
> -#define CONFIG_SPL_STACK 0x95fff0
> -#define CONFIG_SPL_BSS_START_ADDR 0x00950000
> -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
> +#define CONFIG_SPL_STACK 0x980000
> +#define CONFIG_SPL_BSS_START_ADDR 0x950000
> +#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 8 KB */
If ATF sits at 960000 and CONFIG_SPL_BSS_START_ADDR starts at
0x950000, 8K should fit with extra space. I think it should be able
to go even larger.
I took your patch and applied it to the Beacon 8mn kit and, I was able
to set the max size to SZ_64K with CONFIG_SPL_BSS_START_ADDR set to
0x950000
The reference manual states that OCRAM starts at 910000. What is
located in the space between 910000 and 950000?
> #define CONFIG_SYS_SPL_MALLOC_START 0x42200000
> #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
> #define CONFIG_SYS_ICACHE_OFF
> #define CONFIG_SYS_DCACHE_OFF
>
> -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
> -#define CONFIG_MALLOC_F_ADDR 0x00940000
> -
> /* For RAW image gives a error info not panic */
> #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
>
> --
> 2.28.0
>
