Hi Jorge,
On Thu, Jan 16, 2020 at 6:51 PM Fabio Estevam <feste...@gmail.com> wrote:
> Could you please test these two patches? (They were only compiled tested)
Please discard these patches. Just realized that CTRL is at a
different offset for PMC1.
Please try these instead.
From 50d4598ae23c549fe3809bfa5f365364ac36d71b Mon Sep 17 00:00:00 2001
From: Fabio Estevam <feste...@gmail.com>
Date: Thu, 16 Jan 2020 18:59:30 -0300
Subject: [PATCH 1/2] mx7ulp: Fix the PMC register set
On i.MX7ULP the PMC0 registers control the M4 side and
the PMC1 controls the A7 side.
In order to enable the A7 LDO-enabled mode the PMC1 registers
need to configured instead.
Signed-off-by: Fabio Estevam <feste...@gmail.com>
---
arch/arm/mach-imx/mx7ulp/soc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 8345b01398..481cfe226a 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -16,6 +16,7 @@
#define PMC0_CTRL_LDOOKDIS BIT(30)
#define PMC0_CTRL_PMC1ON BIT(24)
#define PMC1_BASE_ADDR 0x40400000
+#define PMC1_CTRL 0x24
#define PMC1_RUN 0x8
#define PMC1_STOP 0x10
#define PMC1_VLPS 0x14
@@ -123,7 +124,7 @@ static void init_ldo_mode(void)
unsigned int reg;
/* Set LDOOKDIS */
- setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
+ setbits_le32(PMC1_BASE_ADDR + PMC1_CTRL, PMC0_CTRL_LDOOKDIS);
/* Set LDOVL to 0.95V in PMC1_RUN */
reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
@@ -149,10 +150,10 @@ static void init_ldo_mode(void)
writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
/* Set LDOEN bit */
- setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
+ setbits_le32(PMC1_BASE_ADDR + PMC1_CTRL, PMC0_CTRL_LDOEN);
/* Set the PMC1ON bit */
- setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
+ setbits_le32(PMC1_BASE_ADDR + PMC1_CTRL, PMC0_CTRL_PMC1ON);
}
#endif
@@ -198,7 +199,7 @@ static bool ldo_mode_is_enabled(void)
{
unsigned int reg;
- reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
+ reg = readl(PMC1_BASE_ADDR + PMC1_CTRL);
if (reg & PMC0_CTRL_LDOEN)
return true;
else
--
2.17.1
From d1a07fb70610184c042df7f593dd0ff8302235c8 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <feste...@gmail.com>
Date: Thu, 16 Jan 2020 19:00:23 -0300
Subject: [PATCH 2/2] mx7ulp: Fix the order for enabling LDO
As per the i.MX7ULP Reference Manual:
"28.5.9.1.1 Using internal LDO regulator
After a POR event, when the PMC 0 is running in RUN mode and the PMC 1 is turned
off, the process to turn on the PMC 1 using the internal LDO regulator
is as follows:
- Assert the LDOEN bit (PMC0_CTRL).
- Assert the LDOOKDIS bit (PMC0_CTRL) if required.
- Assert the PMC1ON bit (PMC0_CTRL)."
So follow the recommended intialization order.
Signed-off-by: Fabio Estevam <feste...@gmail.com>
---
arch/arm/mach-imx/mx7ulp/soc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 481cfe226a..9b114a8604 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -123,9 +123,6 @@ static void init_ldo_mode(void)
{
unsigned int reg;
- /* Set LDOOKDIS */
- setbits_le32(PMC1_BASE_ADDR + PMC1_CTRL, PMC0_CTRL_LDOOKDIS);
-
/* Set LDOVL to 0.95V in PMC1_RUN */
reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
reg &= ~PMC1_LDOVL_MASK;
@@ -152,6 +149,9 @@ static void init_ldo_mode(void)
/* Set LDOEN bit */
setbits_le32(PMC1_BASE_ADDR + PMC1_CTRL, PMC0_CTRL_LDOEN);
+ /* Set LDOOKDIS */
+ setbits_le32(PMC1_BASE_ADDR + PMC1_CTRL, PMC0_CTRL_LDOOKDIS);
+
/* Set the PMC1ON bit */
setbits_le32(PMC1_BASE_ADDR + PMC1_CTRL, PMC0_CTRL_PMC1ON);
}
--
2.17.1
