Hi Jorge,
On Thu, Jan 16, 2020 at 6:33 PM Fabio Estevam <feste...@gmail.com> wrote:
> > I think it is interesting that bit PMC0_CTRL_PMC1ON is already set so
> > I am wondering if you think it is possible - in your experience- that
> > ROM might have already configured LDO? or was this also the case -
> > this bit already set- when you tested the feature?
I think I understand the problem now.
We are currently acessing the PMC0 registers, which control the M4 side.
M4 has LDO enabled set by the ROM, so that's why you see it enabled by default.
We need to access the PMC1 registers instead of PMC0.
Could you please test these two patches? (They were only compiled tested)
Regards,
Fabio Estevam
From bac282ace36ccbb4c46eda03b479eeba6953ff90 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <feste...@gmail.com>
Date: Thu, 16 Jan 2020 18:42:26 -0300
Subject: [PATCH 1/2] mx7ulp: Fix the PMC register set
On i.MX7ULP the PMC0 registers control the M4 side and
the PMC1 controls the A7 side.
In order to enable LDO mode the PMC1 registers need to
configured.
Reported-by: Jorge Ramirez-Ortiz <jo...@foundries.io>
Signed-off-by: Fabio Estevam <feste...@gmail.com>
---
arch/arm/mach-imx/mx7ulp/soc.c | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 8345b01398..f9cfec72b2 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -10,11 +10,10 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/hab.h>
-#define PMC0_BASE_ADDR 0x410a1000
-#define PMC0_CTRL 0x28
-#define PMC0_CTRL_LDOEN BIT(31)
-#define PMC0_CTRL_LDOOKDIS BIT(30)
-#define PMC0_CTRL_PMC1ON BIT(24)
+#define PMC_CTRL 0x28
+#define PMC_CTRL_LDOEN BIT(31)
+#define PMC_CTRL_LDOOKDIS BIT(30)
+#define PMC_CTRL_PMC1ON BIT(24)
#define PMC1_BASE_ADDR 0x40400000
#define PMC1_RUN 0x8
#define PMC1_STOP 0x10
@@ -123,7 +122,7 @@ static void init_ldo_mode(void)
unsigned int reg;
/* Set LDOOKDIS */
- setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
+ setbits_le32(PMC1_BASE_ADDR + PMC_CTRL, PMC_CTRL_LDOOKDIS);
/* Set LDOVL to 0.95V in PMC1_RUN */
reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
@@ -149,10 +148,10 @@ static void init_ldo_mode(void)
writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
/* Set LDOEN bit */
- setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
+ setbits_le32(PMC1_BASE_ADDR + PMC_CTRL, PMC_CTRL_LDOEN);
/* Set the PMC1ON bit */
- setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
+ setbits_le32(PMC1_BASE_ADDR + PMC_CTRL, PMC_CTRL_PMC1ON);
}
#endif
@@ -190,16 +189,15 @@ const char *get_imx_type(u32 imxtype)
return "7ULP";
}
-#define PMC0_BASE_ADDR 0x410a1000
-#define PMC0_CTRL 0x28
-#define PMC0_CTRL_LDOEN BIT(31)
+#define PMC_CTRL 0x28
+#define PMC_CTRL_LDOEN BIT(31)
static bool ldo_mode_is_enabled(void)
{
unsigned int reg;
- reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
- if (reg & PMC0_CTRL_LDOEN)
+ reg = readl(PMC1_BASE_ADDR + PMC_CTRL);
+ if (reg & PMC_CTRL_LDOEN)
return true;
else
return false;
--
2.17.1
From 5c1dca768ef6e8deeb34eccac7e2c8ce06b4ef04 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <feste...@gmail.com>
Date: Thu, 16 Jan 2020 18:43:21 -0300
Subject: [PATCH 2/2] mx7ulp: Fix the order for enabling LDO
As per the i.MX7ULP Reference Manual:
"28.5.9.1.1 Using internal LDO regulator
After a POR event, when the PMC 0 is running in RUN mode and the PMC 1 is turned
off, the process to turn on the PMC 1 using the internal LDO regulator
is as follows:
- Assert the LDOEN bit (PMC0_CTRL).
- Assert the LDOOKDIS bit (PMC0_CTRL) if required.
- Assert the PMC1ON bit (PMC0_CTRL)."
So follow the recommended intialization order.
Signed-off-by: Fabio Estevam <feste...@gmail.com>
---
arch/arm/mach-imx/mx7ulp/soc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index f9cfec72b2..8d232dd894 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -121,9 +121,6 @@ static void init_ldo_mode(void)
{
unsigned int reg;
- /* Set LDOOKDIS */
- setbits_le32(PMC1_BASE_ADDR + PMC_CTRL, PMC_CTRL_LDOOKDIS);
-
/* Set LDOVL to 0.95V in PMC1_RUN */
reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
reg &= ~PMC1_LDOVL_MASK;
@@ -150,6 +147,9 @@ static void init_ldo_mode(void)
/* Set LDOEN bit */
setbits_le32(PMC1_BASE_ADDR + PMC_CTRL, PMC_CTRL_LDOEN);
+ /* Set LDOOKDIS */
+ setbits_le32(PMC1_BASE_ADDR + PMC_CTRL, PMC_CTRL_LDOOKDIS);
+
/* Set the PMC1ON bit */
setbits_le32(PMC1_BASE_ADDR + PMC_CTRL, PMC_CTRL_PMC1ON);
}
--
2.17.1
