Hi Rick,
On Thu, Oct 31, 2019 at 10:31 AM Rick Chen <rickche...@gmail.com> wrote:
>
> Hi Bin
>
> >
> > Hi Rick,
> >
> > On Fri, Oct 25, 2019 at 2:18 PM Andes <ub...@andestech.com> wrote:
> > >
> > > From: Rick Chen <r...@andestech.com>
> > >
> > > The mcache_ctl csr only can be manipulated in M mode.
> > > Add SPL_RISCV_MMODE for U-Boot SPL to control cache
> > > operation.
> > >
> > > Signed-off-by: Rick Chen <r...@andestech.com>
> > > Cc: KC Lin <kc...@andestech.com>
> > > Cc: Alan Kao <alan...@andestech.com>
> > > ---
> > > arch/riscv/cpu/ax25/cache.c | 60
> > > ++++++++++++++++++++++++++++++++++-----------
> > > 1 file changed, 46 insertions(+), 14 deletions(-)
> > >
> > > diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
> > > index 41de30c..9437e81 100644
> > > --- a/arch/riscv/cpu/ax25/cache.c
> > > +++ b/arch/riscv/cpu/ax25/cache.c
> > > @@ -11,18 +11,46 @@
> > > #include <asm/csr.h>
> > >
> > > #ifdef CONFIG_RISCV_NDS_CACHE
> > > +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
> >
> > Use CONFIG_IS_ENABLED(RISCV_MMODE)
> >
> > > /* mcctlcommand */
> > > #define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
> > >
> > > /* D-cache operation */
> > > #define CCTL_L1D_WBINVAL_ALL 6
> > > #endif
> > > +#endif
> > > +
> > > +#ifdef CONFIG_V5L2_CACHE
> > > +static void _cache_enable(void)
> > > +{
> > > + struct udevice *dev = NULL;
> > > +
> > > + uclass_find_first_device(UCLASS_CACHE, &dev);
> > > +
> > > + if (dev)
> > > + cache_enable(dev);
> > > +}
> > > +
> > > +static void _cache_disable(void)
> > > +{
> > > + struct udevice *dev = NULL;
> > > +
> > > + uclass_find_first_device(UCLASS_CACHE, &dev);
> > > +
> > > + if (dev)
> > > + cache_disable(dev);
> > > +}
> > > +#endif
> > >
> > > void flush_dcache_all(void)
> > > {
> > > +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
> > > #ifdef CONFIG_RISCV_NDS_CACHE
> > > +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
> > > csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
> > > #endif
> > > +#endif
> > > +#endif
> > > }
> > >
> > > void flush_dcache_range(unsigned long start, unsigned long end)
> > > @@ -39,6 +67,7 @@ void icache_enable(void)
> > > {
> > > #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
> > > #ifdef CONFIG_RISCV_NDS_CACHE
> > > +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
> > > asm volatile (
> > > "csrr t1, mcache_ctl\n\t"
> > > "ori t0, t1, 0x1\n\t"
> > > @@ -46,12 +75,14 @@ void icache_enable(void)
> > > );
> > > #endif
> > > #endif
> > > +#endif
> > > }
> > >
> > > void icache_disable(void)
> > > {
> > > #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
> > > #ifdef CONFIG_RISCV_NDS_CACHE
> > > +#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
> > > asm volatile (
> > > "fence.i\n\t"
> > > "csrr t1, mcache_ctl\n\t"
> >
> > Could you please add a patch to replace the CSR name with CSR number?
> > This way an upstream GCC to build this code without any issue.
>
> Thanks for your suggestions.
> But I prefer not modify it in this patchs for SPL.
>
Yes, I was saying an additional patch. Definitely not this patch.
> I will send another patch to modify as your suggestions.
Regards,
Bin
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