Hi Vladimir, On Mon, Jun 24, 2019 at 1:50 AM Vladimir Oltean <olte...@gmail.com> wrote: > > From: Jianchao Wang <jianchao.w...@nxp.com> > > The LS1021A-TSN is a development board built by VVDN/Argonboards in > partnership with NXP. > > It features the LS1021A SoC and the first-generation SJA1105T Ethernet > switch for prototyping implementations of a subset of IEEE 802.1 TSN > standards. > > Supported boot media: microSD card (via SPL), QSPI flash. > > Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which > is 64 MB in size and has an erase sector size of 256KB (therefore, > flashing the RCW would erase part of U-boot).
nits: U-Boot > > Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which > is only 32 MB in size but has an erase sector size of 64KB (therefore > the RCW image can be flashed without erasing U-boot). ditto > > To avoid the problems above, the U-boot base address has been selected ditto > at 0x100000 (the start of the 5th 256KB erase sector), which works for > all board revisions. Actually 0x40000 would have been enough, but > 0x100000 is common for all Layerscape devices. > > eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but > SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is > disabled. > > Signed-off-by: Xiaoliang Yang <xiaoliang.y...@nxp.com> > Signed-off-by: Mingkai Hu <mingkai...@nxp.com> > Signed-off-by: Jianchao Wang <jianchao.w...@nxp.com> > Signed-off-by: Changming Huang <jerry.hu...@nxp.com> > > [Vladimir] Code taken from https://github.com/openil/u-boot (which > itself is mostly copied from ls1021a-iot) and adapted with the following > changes: > > - Add a008850 errata workaround > - Converted eTSEC, MMC to DM to avoid all build warnings > - Plugged in distro boot feature, including support for extlinux.conf > - Added defconfig for QSPI boot > - Added the board/freescale/ls1021atsn/README.rst for initial setup > > Signed-off-by: Vladimir Oltean <olte...@gmail.com> > --- > arch/arm/Kconfig | 14 + > arch/arm/dts/Makefile | 2 +- > arch/arm/dts/ls1021a-tsn.dts | 77 ++++ > board/freescale/ls1021atsn/Kconfig | 18 + > board/freescale/ls1021atsn/MAINTAINERS | 8 + > board/freescale/ls1021atsn/Makefile | 3 + > board/freescale/ls1021atsn/README.rst | 96 +++++ > board/freescale/ls1021atsn/ls1021atsn.c | 291 +++++++++++++++ > board/freescale/ls1021atsn/ls102xa_pbi.cfg | 15 + > board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg | 8 + > configs/ls1021atsn_qspi_defconfig | 76 ++++ > configs/ls1021atsn_sdcard_defconfig | 85 +++++ > include/configs/ls1021atsn.h | 346 ++++++++++++++++++ > 13 files changed, 1038 insertions(+), 1 deletion(-) > create mode 100644 arch/arm/dts/ls1021a-tsn.dts > create mode 100644 board/freescale/ls1021atsn/Kconfig > create mode 100644 board/freescale/ls1021atsn/MAINTAINERS > create mode 100644 board/freescale/ls1021atsn/Makefile > create mode 100644 board/freescale/ls1021atsn/README.rst > create mode 100644 board/freescale/ls1021atsn/ls1021atsn.c > create mode 100644 board/freescale/ls1021atsn/ls102xa_pbi.cfg > create mode 100644 board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg > create mode 100644 configs/ls1021atsn_qspi_defconfig > create mode 100644 configs/ls1021atsn_sdcard_defconfig > create mode 100644 include/configs/ls1021atsn.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 01ff57cf1bec..5edac7ea2bd5 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1327,6 +1327,19 @@ config TARGET_LS1021ATWR > select SUPPORT_SPL > imply SCSI > > +config TARGET_LS1021ATSN > + bool "Support ls1021atsn" > + select ARCH_LS1021A > + select ARCH_SUPPORT_PSCI > + select BOARD_EARLY_INIT_F > + select BOARD_LATE_INIT > + select CPU_V7A > + select CPU_V7_HAS_NONSEC > + select CPU_V7_HAS_VIRT > + select LS1_DEEP_SLEEP > + select SUPPORT_SPL > + imply SCSI > + > config TARGET_LS1021AIOT > bool "Support ls1021aiot" > select ARCH_LS1021A > @@ -1693,6 +1706,7 @@ source "board/freescale/ls1028a/Kconfig" > source "board/freescale/ls1021aqds/Kconfig" > source "board/freescale/ls1043aqds/Kconfig" > source "board/freescale/ls1021atwr/Kconfig" > +source "board/freescale/ls1021atsn/Kconfig" > source "board/freescale/ls1021aiot/Kconfig" > source "board/freescale/ls1046aqds/Kconfig" > source "board/freescale/ls1043ardb/Kconfig" > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 528fb909d5b0..28590b0c5530 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -325,7 +325,7 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb > dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ > ls1021a-qds-lpuart.dtb \ > ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ > - ls1021a-iot-duart.dtb > + ls1021a-iot-duart.dtb ls1021a-tsn.dtb > dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ > fsl-ls2080a-rdb.dtb \ > fsl-ls2081a-rdb.dtb \ > diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts > new file mode 100644 > index 000000000000..f633074099dc > --- /dev/null > +++ b/arch/arm/dts/ls1021a-tsn.dts > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright 2016-2018 NXP Semiconductors > + * Copyright 2019 Vladimir Oltean <olte...@gmail.com> > + */ > + > +/dts-v1/; > +#include "ls1021a.dtsi" > + > +/ { > + model = "NXP LS1021A-TSN Board"; > + > + aliases { > + enet0-sgmii-phy = &sgmii_phy2; > + enet1-sgmii-phy = &sgmii_phy1; > + spi0 = &qspi; > + spi1 = &dspi1; > + }; > +}; > + > +&enet0 { > + tbi-handle = <&tbi0>; > + phy-handle = <&sgmii_phy2>; > + phy-mode = "sgmii"; > + status = "okay"; > +}; > + > +&enet1 { > + tbi-handle = <&tbi1>; > + phy-handle = <&sgmii_phy1>; > + phy-mode = "sgmii"; > + status = "okay"; > +}; > + > +&i2c0 { > + status = "okay"; > +}; > + > +&mdio0 { > + /* AR8031 */ > + sgmii_phy1: ethernet-phy@1 { > + reg = <0x1>; > + }; > + > + /* AR8031 */ > + sgmii_phy2: ethernet-phy@2 { > + reg = <0x2>; > + }; > + > + /* SGMII PCS for enet0 */ > + tbi0: tbi-phy@1f { > + reg = <0x1f>; > + device_type = "tbi-phy"; > + }; > +}; > + > +&mdio1 { > + /* SGMII PCS for enet1 */ > + tbi1: tbi-phy@1f { > + reg = <0x1f>; > + device_type = "tbi-phy"; > + }; > +}; > + > +&qspi { > + bus-num = <0>; > + status = "okay"; > + > + flash@0 { > + compatible = "spi-flash"; > + spi-max-frequency = <20000000>; > + reg = <0>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/board/freescale/ls1021atsn/Kconfig > b/board/freescale/ls1021atsn/Kconfig > new file mode 100644 > index 000000000000..d999fa469002 > --- /dev/null > +++ b/board/freescale/ls1021atsn/Kconfig > @@ -0,0 +1,18 @@ > +# SPDX-License-Identifier: GPL-2.0 > +if TARGET_LS1021ATSN > + > +config SYS_BOARD > + default "ls1021atsn" > + > +config SYS_VENDOR > + default "freescale" > + > +config SYS_SOC > + default "ls102xa" > + > +config SYS_CONFIG_NAME > + default "ls1021atsn" > + > +source "board/freescale/common/Kconfig" > + > +endif > diff --git a/board/freescale/ls1021atsn/MAINTAINERS > b/board/freescale/ls1021atsn/MAINTAINERS > new file mode 100644 > index 000000000000..560bb615d2fe > --- /dev/null > +++ b/board/freescale/ls1021atsn/MAINTAINERS > @@ -0,0 +1,8 @@ > +NXP LS1021A-TSN Board > +M: Vladimir Oltean <olte...@gmail.com> > +S: Maintained > +F: arch/arm/dts/ls1021a-tsn.dts > +F: board/freescale/ls1021atsn/ > +F: include/configs/ls1021atsn.h > +F: configs/ls1021atsn_qspi_defconfig > +F: configs/ls1021atsn_sdcard_defconfig > diff --git a/board/freescale/ls1021atsn/Makefile > b/board/freescale/ls1021atsn/Makefile > new file mode 100644 > index 000000000000..b4808f05e8e0 > --- /dev/null > +++ b/board/freescale/ls1021atsn/Makefile > @@ -0,0 +1,3 @@ > +# SPDX-License-Identifier: GPL-2.0 > +obj-y += ls1021atsn.o > +obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o > diff --git a/board/freescale/ls1021atsn/README.rst > b/board/freescale/ls1021atsn/README.rst > new file mode 100644 > index 000000000000..e986f460c4d4 > --- /dev/null > +++ b/board/freescale/ls1021atsn/README.rst > @@ -0,0 +1,96 @@ > +.. SPDX-License-Identifier: GPL-2.0 > + > +LS1021A-TSN Board Overview > +========================== > + > + - 1GB DDR3 at 800 MHz > + - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash > + - Ethernet > + - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031) > + - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R) > + - One internal RGMII port connected to the switch > + - SDHC > + - microSDHC/SDXC connector > + - Other I/O > + - One Serial port > + - Arduino and expansion headers > + - mPCIE slot > + - SATA port > + - USB3.0 port > + > +LS1021A Memory map > +================== > + > +The addresses in brackets are physical addresses. > + > +============== ============== ============================== ======= > +Start Address End Address Description Size > +============== ============== ============================== ======= > +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB > +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB > +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB > +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB > +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB > +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB > +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB > +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB > +============== ============== ============================== ======= > + > +Compiling and flashing > +====================== > + > +The LS1021A-TSN board comes along with a microSD card with OpenIL U-boot. nits: U-Boot > +That will be used to update the internal QSPI flash, as well as > + > +To compile and flash an SD card image:: > + > + make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp > u-boot-with-spl-pbl.bin /srv/tftpboot/ > + => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 > 0x1100 && mmc write 0x82000000 8 0x1100 > + > +For the QSPI flash, first obtain the Reset Configuration Word binary for > +bootimg from the QSPI flash from the rcw project > +(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw):: > + > + make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped > /srv/tftpboot/ > + > +The above RCW binary takes care of swapping the QSPI AMBA memory, so that the > +U-boot binary does not need to be swapped when flashing it. nits: U-Boot > + > +To compile and flash a U-boot image for QSPI:: ditto > + > + make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin > /srv/tftpboot/ > + > +Then optionally create a custom uboot-env.txt file (although the default > +environment already supports distro boot) and convert it to binary format:: > + > + mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt > + > +To program the QSPI flash with the images:: > + > + => tftp 0x82000000 rcw_1000_qspiboot.bin.swapped && sf probe && sf erase > 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize} > + => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 > +${filesize} && sf write 0x82000000 0x100000 ${filesize} > + => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 > +${filesize} && sf write 0x82000000 0x400000 ${filesize} > + > +The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC > +addresses of the Ethernet interfaces, however the EEPROM comes blank out of > +the factory, and the MAC addresses are printed on a label on the bottom of > +the boards. > + > +To write the MAC addresses to the EEPROM, the following needs to be done > once:: > + > + => mac id > + => mac 0 00:1F:7B:xx:xx:xx > + => mac 1 00:1F:7B:xx:xx:xx > + => mac 2 00:1F:7B:xx:xx:xx > + => mac save > + > +The switch ports do not have their own MAC address - they inherit it from the > +master enet2 port. > + > +Known issues and limitations > +============================ > + > +- The 4 SJA1105 switch ports are not functional in U-boot for now. nits: U-Boot > +- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is > + no way to talk to the CPLD for e.g. running the "qixis_reset" command, or > + turning the fan on, etc. > diff --git a/board/freescale/ls1021atsn/ls1021atsn.c > b/board/freescale/ls1021atsn/ls1021atsn.c > new file mode 100644 > index 000000000000..84c2af142956 > --- /dev/null > +++ b/board/freescale/ls1021atsn/ls1021atsn.c > @@ -0,0 +1,291 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Copyright 2016-2019 NXP Semiconductors > + */ > +#include <common.h> > +#include <i2c.h> > +#include <asm/io.h> > +#include <asm/arch/immap_ls102xa.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/fsl_serdes.h> > +#include <asm/arch-ls102xa/ls102xa_soc.h> > +#include <asm/arch/ls102xa_devdis.h> > +#include <asm/arch/ls102xa_soc.h> > +#include <hwconfig.h> > +#include <mmc.h> > +#include <fsl_csu.h> > +#include <fsl_esdhc.h> > +#include <fsl_ifc.h> > +#include <fsl_immap.h> > +#include <netdev.h> > +#include <spl.h> > +#include "../common/sleep.h" > +#ifdef CONFIG_U_QE > +#include <fsl_qe.h> > +#endif > +#include <fsl_validate.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +void cpld_show(void) This should be static. > +{ > + struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; > + u32 cpldrev; > + int major; > + int minor; > + > + cpldrev = in_be32(&dcfg->gpporcr1); > + major = (cpldrev >> 28) & 0xf; > + minor = (cpldrev >> 24) & 0xf; > + > + printf("CPLD: V%d.%d\n", major, minor); > +} > + > +int checkboard(void) > +{ > + puts("Board: LS1021ATSN\n"); > + cpld_show(); > + return 0; > +} > + > +void ddrmc_init(void) This should be static. > +{ > + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; > + u32 temp_sdram_cfg, tmp; > + > + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); > + > + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); > + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); > + > + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); > + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); > + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); > + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); > + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); > + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); > + > +#ifdef CONFIG_DEEP_SLEEP > + if (is_warm_boot()) { > + out_be32(&ddr->sdram_cfg_2, > + DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); > + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); > + out_be32(&ddr->init_ext_addr, (1 << 31)); > + > + /* DRAM VRef will not be trained */ > + out_be32(&ddr->ddr_cdr2, > + DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); > + } else > +#endif > + { > + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); > + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); > + } > + > + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); > + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); > + > + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); > + > + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); > + > + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); > + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); > + > + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); > + > + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); > + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); > + > + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); > + > + /* DDR erratum A-009942 */ > + tmp = in_be32(&ddr->debug[28]); > + out_be32(&ddr->debug[28], tmp | 0x0070006f); > + > + udelay(1); > + > +#ifdef CONFIG_DEEP_SLEEP > + if (is_warm_boot()) { > + /* enter self-refresh */ > + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); > + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; > + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); > + > + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); > + } else > +#endif > + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); > + > + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); > + > +#ifdef CONFIG_DEEP_SLEEP > + if (is_warm_boot()) { > + /* exit self-refresh */ > + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); > + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; > + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); > + } > +#endif > +} > + > +int dram_init(void) > +{ > +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) > + ddrmc_init(); > +#endif > + > + erratum_a008850_post(); > + > + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > + > +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) > + fsl_dp_resume(); > +#endif > + > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > + return pci_eth_init(bis); > +} > + > +int board_early_init_f(void) > +{ > + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; > + > +#ifdef CONFIG_TSEC_ENET > + /* Clear BD & FR bits for big endian BD's and frame data (aka set > + * correct eTSEC endianness). This is crucial in ensuring that it does > + * not report Data Parity Errors in its RX/TX FIFOs when attempting to > + * send traffic. > + */ > + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); > + /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */ > + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); > +#endif > + > +#ifdef CONFIG_FSL_IFC > + init_early_memctl_regs(); > +#endif > + > + arch_soc_init(); > + > +#if defined(CONFIG_DEEP_SLEEP) > + if (is_warm_boot()) { > + timer_init(); > + dram_init(); > + } > +#endif > + > + return 0; > +} > + > +#ifdef CONFIG_SPL_BUILD > +void board_init_f(ulong dummy) > +{ > + void (*second_uboot)(void); > + > + /* Clear the BSS */ > + memset(__bss_start, 0, __bss_end - __bss_start); > + > + get_clocks(); > + > +#if defined(CONFIG_DEEP_SLEEP) > + if (is_warm_boot()) > + fsl_dp_disable_console(); > +#endif > + > + preloader_console_init(); > + > + dram_init(); > + > + /* Allow OCRAM access permission as R/W */ > +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS > + enable_layerscape_ns_access(); > + enable_layerscape_ns_access(); > +#endif > + > + /* > + * if it is woken up from deep sleep, then jump to second > + * stage uboot and continue executing without recopying > + * it from SD since it has already been reserved in memory > + * in last boot. > + */ > + if (is_warm_boot()) { > + second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; > + second_uboot(); > + } > + > + board_init_r(NULL, 0); > +} > +#endif > + > +int board_init(void) > +{ > +#ifndef CONFIG_SYS_FSL_NO_SERDES > + fsl_serdes_init(); > +#endif > + ls102xa_smmu_stream_id_init(); > + > +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS > + enable_layerscape_ns_access(); > +#endif > + > +#ifdef CONFIG_U_QE > + u_qe_init(); > +#endif > + > + return 0; > +} > + > +#if defined(CONFIG_SPL_BUILD) > +void spl_board_init(void) > +{ > + ls102xa_smmu_stream_id_init(); > +} > +#endif > + > +#ifdef CONFIG_BOARD_LATE_INIT > +int board_late_init(void) > +{ > +#ifdef CONFIG_CHAIN_OF_TRUST > + fsl_setenv_chain_of_trust(); > +#endif > + > + return 0; > +} > +#endif > + > +#if defined(CONFIG_MISC_INIT_R) > +int misc_init_r(void) > +{ > +#ifdef CONFIG_FSL_DEVICE_DISABLE > + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); > +#endif > + > +#ifdef CONFIG_FSL_CAAM > + return sec_init(); > +#endif > +} > +#endif > + > +#if defined(CONFIG_DEEP_SLEEP) > +void board_sleep_prepare(void) > +{ > +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS > + enable_layerscape_ns_access(); > +#endif > +} > +#endif > + > +int ft_board_setup(void *blob, bd_t *bd) > +{ > + ft_cpu_setup(blob, bd); > + > +#ifdef CONFIG_PCI > + ft_pci_setup(blob, bd); > +#endif > + > + return 0; > +} [snip] Regards, Bin _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
