DM_I2C_COMPAT is a compatibility layer that allows using the non-DM
I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for
compilation, a compilation error will be generated. This patch
solves the problem that the i2c-related api of the ls1088a platform
does not support dm.
Signed-off-by: Chuanhua Han <chuanhua....@nxp.com>
---
depends on:
- http://patchwork.ozlabs.org/project/uboot/list/?series=110856
- http://patchwork.ozlabs.org/project/uboot/list/?series=109459
Changes in v2:
- No change.
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 -
board/freescale/ls1088a/ls1088a.c | 148 +++++++++++++++++++++++++++++
include/configs/ls1088a_common.h | 3 -
include/configs/ls1088ardb.h | 2 -
4 files changed, 148 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ffda02a..568756d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -155,10 +155,6 @@ config ARCH_LS1088A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
- select SYS_I2C_MXC_I2C1
- select SYS_I2C_MXC_I2C2
- select SYS_I2C_MXC_I2C3
- select SYS_I2C_MXC_I2C4
imply SCSI
imply PANIC_HANG
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..2bac070 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -373,7 +373,15 @@ int select_i2c_ch_pca9547(u8 ch)
{
int ret;
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, 0, &ch, 1);
+#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@@ -392,38 +400,89 @@ void board_retimer_init(void)
/* Access to Control/Shared register */
reg = 0x0;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+#else
+ struct udevice *dev;
+
+ i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 1, ®, 1);
+#endif
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0, ®, 1);
+#endif
reg |= 0x4;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0, ®, 1);
+#endif
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x60, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x61, ®, 1);
+#endif
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x62, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x63, ®, 1);
+#endif
reg = 0xcd;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x64, ®, 1);
+#endif
/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0x2F, ®, 1);
+#endif
reg &= 0x0f;
reg |= 0x70;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x2F, ®, 1);
+#endif
#ifdef CONFIG_TARGET_LS1088AQDS
/* Retimer is connected to I2C1_CH5 */
@@ -431,38 +490,88 @@ void board_retimer_init(void)
/* Access to Control/Shared register */
reg = 0x0;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
+#else
+ i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Read device revision and ID */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 1, ®, 1);
+#endif
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0xff, ®, 1);
+#endif
/* Reset Channel Registers */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0, ®, 1);
+#endif
reg |= 0x4;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0, ®, 1);
+#endif
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x60, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x61, ®, 1);
+#endif
reg = 0x90;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x62, ®, 1);
+#endif
reg = 0xb3;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x63, ®, 1);
+#endif
reg = 0xcd;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x64, ®, 1);
+#endif
/* Select VCO Divider to full rate (000) */
+#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_read(dev, 0x2F, ®, 1);
+#endif
reg &= 0x0f;
reg |= 0x70;
+#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
+#else
+ dm_i2c_write(dev, 0x2F, ®, 1);
+#endif
+
#endif
/*return the default channel*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -499,16 +608,30 @@ int get_serdes_volt(void)
u8 chan = PWM_CHANNEL0;
/* Select the PAGE 0 using PMBus commands PAGE for VDD */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
+ &chan, 1);
+#endif
+
if (ret) {
printf("VID: failed to select VDD Page 0\n");
return ret;
}
/* Read the output voltage using PMBus command READ_VOUT */
+#ifndef CONFIG_DM_I2C
ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
+#else
+ dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
+#endif
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
@@ -524,8 +647,17 @@ int set_serdes_volt(int svdd)
svdd & 0xFF, (svdd & 0xFF00) >> 8};
/* Write the desired voltage code to the SVDD regulator */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
+ (void *)&buff, 5);
+#endif
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@@ -556,8 +688,18 @@ int set_serdes_volt(int svdd)
printf("SVDD changing of RDB\n");
/* Read the BRDCFG54 via CLPD */
+#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+ struct udevice *dev;
+
+ ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
+ if (!ret)
+ ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
+ (void *)&brdcfg4, 1);
+#endif
+
if (ret) {
printf("VID: I2C failed to read the CPLD BRDCFG4\n");
return -1;
@@ -566,8 +708,14 @@ int set_serdes_volt(int svdd)
brdcfg4 = brdcfg4 | 0x08;
/* Write to the BRDCFG4 */
+#ifndef CONFIG_DM_I2C
ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
+#else
+ ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
+ (void *)&brdcfg4, 1);
+#endif
+
if (ret) {
debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
return -1;
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index e8e1dc2..53e0b4b 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -66,9 +66,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
-/* I2C */
-#define CONFIG_SYS_I2C
-
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
index 322adb5..b71f704 100644
--- a/include/configs/ls1088ardb.h
+++ b/include/configs/ls1088ardb.h
@@ -269,9 +269,7 @@
* RTC configuration
*/
#define RTC
-#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-#define CONFIG_CMD_DATE
#endif
/* EEPROM */
--
1.7.1
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