On 1/2/19 12:37 AM, Lukasz Majewski wrote:
> With the current code, it is not possible to assign different than default
> numbers for mmc controllers.
>
> Several in-tree boards depend on the pre-dm setup, corresponding to
> following aliases:
>
> mmc0 = &usdhc2; --> fsl,usdhc-index = <1>
> mmc1 = &usdhc4; --> fsl,usdhc-index = <3>
>
> Without this patch we are either forced to use default aliasing - like:
>
> mmc0 = &usdhc1;
> mmc1 = &usdhc2;
> mmc2 = &usdhc3;
> mmc3 = &usdhc4;
>
> to have the proper clocks setup for the controller. However, such setup
> is not acceptable for some legacy scripts / code.
>
> With this patch - by introducing 'fsl,usdhc-index' - one can configure
> (get) clock rate corresponding to used controller.
>
> Moreover, as this code is used in the SPL before relocation (and to save
> space we strip the SPL DTS from clocks and its names) adding separate
> properties seems to be the best approach here. One also avoids adding
> clocks DM code to SPL.
>
> Signed-off-by: Lukasz Majewski <lu...@denx.de>
> ---
>
> drivers/mmc/fsl_esdhc.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 3cdfa7f5a6..49a6834a98 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -1401,6 +1401,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
> fdt_addr_t addr;
> unsigned int val;
> struct mmc *mmc;
> + int usdhc_idx;
> int ret;
>
> addr = dev_read_addr(dev);
> @@ -1513,7 +1514,21 @@ static int fsl_esdhc_probe(struct udevice *dev)
>
> priv->sdhc_clk = clk_get_rate(&priv->per_clk);
> } else {
> - priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
> + /*
> + * Check for 'fsl,index' DTS property - as one may want to have
> + * following mmc setup:
NAK, DT is a hardware description. This is encoding a policy, which
should not be in DT.
This looks like some reimplementation of SEQ_ALIAS stuff.
> + * mmc0 = &usdhc2; --> fsl,index = <1>
> + * mmc1 = &usdhc4; --> fsl,index = <3>
> + *
> + * So we do have dev->seq = {0, 1}, which in the below code
> + * doesn't correspond to correct USDHC clocks.
> + *
> + * For that reason a new "fsl,index" property has been
> + * introduced.
> + */
> + usdhc_idx = dev_read_u32_default(dev, "fsl,usdhc-index",
> + dev->seq);
> + priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + usdhc_idx);
> if (priv->sdhc_clk <= 0) {
> dev_err(dev, "Unable to get clk for %s\n", dev->name);
> return -EINVAL;
>
--
Best regards,
Marek Vasut
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