On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer <lukas.a...@aisec.fraunhofer.de> wrote: > > RISC-V does not guarantee that stores to instruction memory are visible > to instruction fetches (i.e. incoherent instruction caches). Invalidate > the instruction cache to ensure the kernel function pointer points to > the correct memory location. > > Signed-off-by: Lukas Auer <lukas.a...@aisec.fraunhofer.de> > --- > > Changes in v2: > - Clarify reasoning behind patch in commit message > > arch/riscv/lib/bootm.c | 1 + > 1 file changed, 1 insertion(+) >
Reviewed-by: Bin Meng <bmeng...@gmail.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
