Dear Fabio, I checked my PHY KSZ9021 schematic (we used i.mx6 Dual Light) with boundary devices sabre_light_revD(they used i.mx6 quad) KSZ9021. We both use same clock and data signals on both i.mx6 and PHY sides.
I saw 6.25 MHz clock signal on RGMII_TXCLK pin of i.mx6dl which is connected to the GTX_CLK input pin of PHY same as in sabre light. PHY is multiplying this clock with 5 and generating 31.25 MHz, which is connected back to the ENET_REF_CLK pin of i.mx6dl. I guess either my global ethernet clock or its pll clock registers or their mask registers are not set correctly, to generate 25 MHz, instead of 6.25 MHz. May be you know, how may I correct them? Thanks and best regards. Mehmet Ali -----Original Message----- From: Fabio Estevam [mailto:feste...@gmail.com] Sent: Wednesday, January 24, 2018 3:29 PM To: Mehmet Ali İPİN <mehmet.i...@pavotek.com.tr> Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] FW: u-boot v2016 vs v2013 On Wed, Jan 24, 2018 at 10:26 AM, Mehmet Ali İPİN <mehmet.i...@pavotek.com.tr> wrote: > Dear Estevam, > > I am (in fact hardware engineer developed the PCB) not an experienced > u-boot/linux developer, therefore sorry for my complex questions. > I will check the forum, and google for this message, but you may help me to > start the right path. > > May be, according to your experience you can advise me to check some > (phy/mac) register, pin status, clock values, Or give the name of threads in > u-boot or nxp imx6 forum which is about similar dhcp events, if you remember. > > Since its a new PCB board, so we did not load/run the linux yet. Try looking at existing supported boards that use KSZ9021, such as board/boundary/nitrogen6x/nitrogen6x.c for example. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
