From: Chin Liang See <chin.liang....@intel.com>
Add Reset Manager driver support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang....@intel.com>
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
.../include/mach/reset_manager_arria10.h | 8 +-
.../mach-socfpga/include/mach/reset_manager_s10.h | 116 ++++++++++++++++++++
arch/arm/mach-socfpga/reset_manager.c | 41 +++++++
arch/arm/mach-socfpga/reset_manager_arria10.c | 67 +++---------
arch/arm/mach-socfpga/reset_manager_gen5.c | 33 ------
arch/arm/mach-socfpga/reset_manager_s10.c | 118 +++++++++++++++++++++
include/dt-bindings/reset/altr,rst-mgr-s10.h | 97 +++++++++++++++++
9 files changed, 395 insertions(+), 88 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
create mode 100644 arch/arm/mach-socfpga/reset_manager_s10.c
create mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e5f9dd7..f10b05c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,6 +32,7 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
+obj-y += reset_manager_s10.o
obj-y += wrap_pll_config_s10.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6591745..577fcce 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -45,6 +45,8 @@ void socfpga_per_reset_all(void);
#include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/reset_manager_s10.h>
#endif
#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index b6d7f4f..e521839 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -28,10 +28,10 @@ struct socfpga_reset_manager {
u32 hdskreq;
u32 hdskack;
u32 counts;
- u32 mpumodrst;
- u32 per0modrst;
- u32 per1modrst;
- u32 brgmodrst;
+ u32 mpu_mod_reset;
+ u32 per_mod_reset;
+ u32 per2_mod_reset;
+ u32 brg_mod_reset;
u32 sysmodrst;
u32 coldmodrst;
u32 nrstmodrst;
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
new file mode 100644
index 0000000..07ada59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _RESET_MANAGER_S10_
+#define _RESET_MANAGER_S10_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+void socfpga_bridges_reset(int enable);
+
+void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
+
+struct socfpga_reset_manager {
+ u32 status;
+ u32 mpu_rst_stat;
+ u32 misc_stat;
+ u32 padding1;
+ u32 hdsk_en;
+ u32 hdsk_req;
+ u32 hdsk_ack;
+ u32 hdsk_stall;
+ u32 mpu_mod_reset;
+ u32 per_mod_reset; /* stated as per0_mod_reset in S10 datasheet */
+ u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+ u32 brg_mod_reset;
+ u32 padding2;
+ u32 cold_mod_reset;
+ u32 padding3;
+ u32 dbg_mod_reset;
+ u32 tap_mod_reset;
+ u32 padding4;
+ u32 padding5;
+ u32 brg_warm_mask;
+ u32 padding6[3];
+ u32 tst_stat;
+ u32 padding7;
+ u32 hdsk_timeout;
+ u32 mpul2flushtimeout;
+ u32 dbghdsktimeout;
+};
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK 0x7
+#define RSTMGR_RESET_OFFSET 0
+#define RSTMGR_RESET_MASK 0x1f
+#define RSTMGR_DEFINE(_bank, _offset) \
+ ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset) \
+ (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset) \
+ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
+#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
+#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
+#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
+#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
+#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
+#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
+#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
+#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
+#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
+#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
+#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
+#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
+#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
+#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
+#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
+#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
+#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
+#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
+#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
+
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state);
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name) RSTMGR_##_name
+
+#endif /* _RESET_MANAGER_S10_ */
diff --git a/arch/arm/mach-socfpga/reset_manager.c
b/arch/arm/mach-socfpga/reset_manager.c
index 29438ed..6a62e93 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -20,8 +20,13 @@ static const struct socfpga_reset_manager
*reset_manager_base =
void reset_cpu(ulong addr)
{
/* request a warm reset */
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+ writel((1 << RSTMGR_MPUMODRST_CORE0),
+ &reset_manager_base->mpu_mod_reset);
+#else
writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
&reset_manager_base->ctrl);
+#endif
/*
* infinite loop here as watchdog will trigger and reset
* the processor
@@ -29,3 +34,39 @@ void reset_cpu(ulong addr)
while (1)
;
}
+
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+ const u32 *reg = 0;
+ u32 rstmgr_bank = RSTMGR_BANK(reset);
+
+ switch (rstmgr_bank) {
+ case 0:
+ reg = &reset_manager_base->mpu_mod_reset;
+ break;
+ case 1:
+ reg = &reset_manager_base->per_mod_reset;
+ break;
+ case 2:
+ reg = &reset_manager_base->per2_mod_reset;
+ break;
+ case 3:
+ reg = &reset_manager_base->brg_mod_reset;
+ break;
+ case 4:
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+ reg = &reset_manager_base->misc_mod_reset;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+ reg = &reset_manager_base->sysmodrst;
+#endif
+ break;
+ default:
+ return;
+ }
+
+ if (set)
+ setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ else
+ clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 66f1ec2..bf0345c 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -129,14 +129,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
void socfpga_watchdog_disable(void)
{
/* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per1modrst,
+ setbits_le32(&reset_manager_base->per2_mod_reset,
ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}
/* Release NOC ddr scheduler from reset */
void socfpga_reset_deassert_noc_ddr_scheduler(void)
{
- clrbits_le32(&reset_manager_base->brgmodrst,
+ clrbits_le32(&reset_manager_base->brg_mod_reset,
ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
}
@@ -145,7 +145,7 @@ int socfpga_is_wdt_in_reset(void)
{
u32 val;
- val = readl(&reset_manager_base->per1modrst);
+ val = readl(&reset_manager_base->per2_mod_reset);
val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
/* return 0x1 if watchdog in reset */
@@ -181,12 +181,12 @@ void socfpga_emac_manage_reset(ulong emacbase, u32 state)
if (state) {
/* Enable ECC OCP first */
- setbits_le32(&reset_manager_base->per0modrst, eccmask);
- setbits_le32(&reset_manager_base->per0modrst, emacmask);
+ setbits_le32(&reset_manager_base->per_mod_reset, eccmask);
+ setbits_le32(&reset_manager_base->per_mod_reset, emacmask);
} else {
/* Disable ECC OCP first */
- clrbits_le32(&reset_manager_base->per0modrst, emacmask);
- clrbits_le32(&reset_manager_base->per0modrst, eccmask);
+ clrbits_le32(&reset_manager_base->per_mod_reset, emacmask);
+ clrbits_le32(&reset_manager_base->per_mod_reset, eccmask);
}
}
@@ -219,7 +219,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
/* Release bridges from reset state per handoff value */
- clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
+ clrbits_le32(&reset_manager_base->brg_mod_reset, mask_rstmgr);
/* Poll until all idleack to 0, timeout at 1000ms */
return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
@@ -241,54 +241,19 @@ void socfpga_reset_assert_fpga_connected_peripherals(void)
fpga_pinux_addr += sizeof(u32);
}
- setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
- setbits_le32(&reset_manager_base->per1modrst, mask1);
- setbits_le32(&reset_manager_base->per0modrst, mask0);
+ setbits_le32(&reset_manager_base->per_mod_reset, mask0 & ECC_MASK);
+ setbits_le32(&reset_manager_base->per2_mod_reset, mask1);
+ setbits_le32(&reset_manager_base->per_mod_reset, mask0);
}
/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
void socfpga_reset_deassert_osc1wd0(void)
{
- clrbits_le32(&reset_manager_base->per1modrst,
+ clrbits_le32(&reset_manager_base->per2_mod_reset,
ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}
/*
- * Assert or de-assert SoCFPGA reset manager reset.
- */
-void socfpga_per_reset(u32 reset, int set)
-{
- const u32 *reg;
- u32 rstmgr_bank = RSTMGR_BANK(reset);
-
- switch (rstmgr_bank) {
- case 0:
- reg = &reset_manager_base->mpumodrst;
- break;
- case 1:
- reg = &reset_manager_base->per0modrst;
- break;
- case 2:
- reg = &reset_manager_base->per1modrst;
- break;
- case 3:
- reg = &reset_manager_base->brgmodrst;
- break;
- case 4:
- reg = &reset_manager_base->sysmodrst;
- break;
-
- default:
- return;
- }
-
- if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
- else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
-}
-
-/*
* Assert reset on every peripheral but L4WD0.
* Watchdog must be kept intact to prevent glitches
* and/or hangs.
@@ -310,11 +275,11 @@ void socfpga_per_reset_all(void)
ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
- writel(~l4wd0, &reset_manager_base->per1modrst);
- setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
+ writel(~l4wd0, &reset_manager_base->per2_mod_reset);
+ setbits_le32(&reset_manager_base->per_mod_reset, ~mask_ecc_ocp);
/* Finally disable the ECC_OCP */
- setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
+ setbits_le32(&reset_manager_base->per_mod_reset, mask_ecc_ocp);
}
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
@@ -367,7 +332,7 @@ int socfpga_bridges_reset(void)
return ret;
/* Put all bridges (except NOR DDR scheduler) into reset state */
- setbits_le32(&reset_manager_base->brgmodrst,
+ setbits_le32(&reset_manager_base->brg_mod_reset,
(ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c
b/arch/arm/mach-socfpga/reset_manager_gen5.c
index aa88adb..0abb519 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -18,39 +18,6 @@ static const struct socfpga_reset_manager
*reset_manager_base =
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Assert or de-assert SoCFPGA reset manager reset. */
-void socfpga_per_reset(u32 reset, int set)
-{
- const u32 *reg;
- u32 rstmgr_bank = RSTMGR_BANK(reset);
-
- switch (rstmgr_bank) {
- case 0:
- reg = &reset_manager_base->mpu_mod_reset;
- break;
- case 1:
- reg = &reset_manager_base->per_mod_reset;
- break;
- case 2:
- reg = &reset_manager_base->per2_mod_reset;
- break;
- case 3:
- reg = &reset_manager_base->brg_mod_reset;
- break;
- case 4:
- reg = &reset_manager_base->misc_mod_reset;
- break;
-
- default:
- return;
- }
-
- if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
- else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
-}
-
/*
* Assert reset on every peripheral but L4WD0.
* Watchdog must be kept intact to prevent glitches
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
b/arch/arm/mach-socfpga/reset_manager_s10.c
new file mode 100644
index 0000000..2dc050c
--- /dev/null
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+ (void *)SOCFPGA_RSTMGR_ADDRESS;
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+ const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+ /* disable all except OCP and l4wd0. OCP disable later */
+ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
+ &reset_manager_base->per_mod_reset);
+ writel(~l4wd0, &reset_manager_base->per_mod_reset);
+ writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+}
+
+void socfpga_bridges_reset(int enable)
+{
+ if (enable) {
+ /* clear idle request to all bridges */
+ setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
+
+ /* Release bridges from reset state per handoff value */
+ clrbits_le32(&reset_manager_base->brg_mod_reset, ~0);
+
+ /* Poll until all idleack to 0 */
+ while (readl(&system_manager_base->noc_idleack))
+ ;
+ } else {
+ /* set idle request to all bridges */
+ writel(~0, &system_manager_base->noc_idlereq_set);
+
+ /* Enable the NOC timeout */
+ writel(1, &system_manager_base->noc_timeout);
+
+ /* Poll until all idleack to 1 */
+ while ((readl(&system_manager_base->noc_idleack) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+ ;
+
+ /* Poll until all idlestatus to 1 */
+ while ((readl(&system_manager_base->noc_idlestatus) ^
+ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
+ ;
+
+ /* Put all bridges (except NOR DDR scheduler) into reset */
+ setbits_le32(&reset_manager_base->brg_mod_reset,
+ ~RSTMGR_BRGMODRST_DDRSCH_MASK);
+
+ /* Disable NOC timeout */
+ writel(0, &system_manager_base->noc_timeout);
+ }
+}
+
+/* of_reset_id: emac reset id
+ * state: 0 - disable reset, !0 - enable reset
+ */
+void socfpga_emac_manage_reset(const unsigned int of_reset_id, u32 state)
+{
+ u32 reset_emac;
+ u32 reset_emacocp;
+
+ /* hardcode this now */
+ switch (of_reset_id) {
+ case EMAC0_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC0);
+ reset_emacocp = SOCFPGA_RESET(EMAC0_OCP);
+ break;
+ case EMAC1_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC1);
+ reset_emacocp = SOCFPGA_RESET(EMAC1_OCP);
+ break;
+ case EMAC2_RESET:
+ reset_emac = SOCFPGA_RESET(EMAC2);
+ reset_emacocp = SOCFPGA_RESET(EMAC2_OCP);
+ break;
+ default:
+ printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+ hang();
+ break;
+ }
+
+ /* Reset ECC OCP first */
+ socfpga_per_reset(reset_emacocp, state);
+
+ /* Release the EMAC controller from reset */
+ socfpga_per_reset(reset_emac, state);
+}
+
+/*
+ * Release peripherals from reset based on handoff
+ */
+void reset_deassert_peripherals_handoff(void)
+{
+ writel(0, &reset_manager_base->per2_mod_reset);
+ /* Enable OCP first */
+ writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per_mod_reset);
+ writel(0, &reset_manager_base->per_mod_reset);
+}
diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h
b/include/dt-bindings/reset/altr,rst-mgr-s10.h
new file mode 100644
index 0000000..29eb829
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define CPU2_RESET 2
+#define CPU3_RESET 3
+
+/* PER0MODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define EMAC2_RESET 34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+/* 38 is empty*/
+#define SDMMC_RESET 39
+#define EMAC0OCP_RESET 40
+#define EMAC1OCP_RESET 41
+#define EMAC2OCP_RESET 42
+#define USB0OCP_RESET 43
+#define USB1OCP_RESET 44
+#define NANDOCP_RESET 45
+/* 46 is empty*/
+#define SDMMCOCP_RESET 47
+#define DMA_RESET 48
+#define SPIM0_RESET 49
+#define SPIM1_RESET 50
+#define SPIS0_RESET 51
+#define SPIS1_RESET 52
+#define DMAOCP_RESET 53
+#define EMACPTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET 56
+#define DMAIF1_RESET 57
+#define DMAIF2_RESET 58
+#define DMAIF3_RESET 59
+#define DMAIF4_RESET 60
+#define DMAIF5_RESET 61
+#define DMAIF6_RESET 62
+#define DMAIF7_RESET 63
+
+/* PER1MODRST */
+#define L4WD0_RESET 64
+#define L4WD1_RESET 65
+#define L4WD2_RESET 66
+#define L4WD3_RESET 67
+#define L4SYSTIMER0_RESET 68
+#define L4SYSTIMER1_RESET 69
+#define SPTIMER0_RESET 70
+#define SPTIMER1_RESET 71
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET 80
+#define UART1_RESET 81
+/* 82-87 is reserved */
+#define GPIO0_RESET 88
+#define GPIO1_RESET 89
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET 99
+#define F2SSDRAM1_RESET 100
+#define F2SSDRAM2_RESET 101
+#define DDRSCH_RESET 102
+
+/* 128-159 is reserved */
+
+/* COLDMODRST */
+#define CPUPOR0_RESET 160
+#define CPUPOR1_RESET 161
+#define CPUPOR2_RESET 162
+#define CPUPOR3_RESET 163
+/* 164-167 is reserved */
+#define L2_RESET 168
+
+/* 192-223 is reserved */
+
+/* DBGMODRST */
+#define DBG_RESET 224
+#define CSDAP_RESET 225
+
+#endif
--
2.2.2
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