Hi Bin,
On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng...@gmail.com> wrote:
> Hi Jagan,
>
> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.t...@gmail.com> wrote:
>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng...@gmail.com> wrote:
>>> On some flash (like Macronix), QE (quad enable) bit is in the same
>>> status register as BP# bits, and we need preserve its original value
>>> during a reboot cycle as this is required by some platforms (like
>>> Intel ICH SPI controller working under descriptor mode).
>>>
>>> Signed-off-by: Bin Meng <bmeng...@gmail.com>
>>> ---
>>>
>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++--
>>> 1 file changed, 15 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
>>> index 0034a28..7d8c660 100644
>>> --- a/drivers/mtd/spi/spi_flash.c
>>> +++ b/drivers/mtd/spi/spi_flash.c
>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash)
>>> if (IS_ERR_OR_NULL(info))
>>> return -ENOENT;
>>>
>>> - /* Flash powers up read-only, so clear BP# bits */
>>> + /*
>>> + * Flash powers up read-only, so clear BP# bits.
>>> + *
>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in
>>> the
>>> + * same status register as BP# bits, and we need preserve its
>>> original
>>> + * value during a reboot cycle as this is required by some platforms
>>> + * (like Intel ICH SPI controller working under descriptor mode).
>>> + */
>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
>>> write_sr(flash, 0);
>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) {
>>> + u8 sr = 0;
>>> +
>>> + read_sr(flash, &sr);
>>> + sr &= STATUS_QEB_MXIC;
>>> + write_sr(flash, sr);
>>> + }
>>
>> It doesn't make sense to have one(specific) controller fix to be
>> generic to all macronix chips, think about alternative.
>>
>
> This is no way to fix at the controller level. Actually this is
> nothing related to controller level. It's just the bootstrap settings
> (QE bit in this case) that cannot be overwritten by someone else
> (although it's seen on Intel, it might happen on some other
> architecture). The logic in the codes are having issues. Its comment
> says: clear BP# bits, but it clears QE bit for Macronix flash as well,
> which is wrong. The update was just to make sure the codes do as what
> its comment says.
I believe QEB is same position for all Macronix chips, checked few
parts true? what if the supported chips from id tables doesn't have
QEB at-all means specific chip support upto dual?
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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